Senior Hardware Power Test Engineer, Platforms Infrastructure

Socket.dev; Sunnyvale (CA); On-site; USD 159,000 - 230,000; Full time

Benefits offered by this job

Equity

Bonus target

Benefits

Job summary

Google in Sunnyvale, CA is seeking a Senior Hardware Test Engineer to lead electrical characterization, validation and qualification of server power systems from converter design to ASIC power integrity validation.

You will collaborate with HW design and lab teams, develop automated test procedures, analyze data, and drive lab readiness for new products entering R&D, with focus on power measurement equipment and bench-level HW validation.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, or related field, or equivalent practical experience.
• 4 years of experience in a power electronics technical environment, or 3 years with an advanced degree.
• Master's degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field.
• 1 year of experience in technical leadership.
• Experience with power measurement equipment such as oscilloscopes, programmable power supplies, spectrum analyzers, DMMs and function generators.
• Proficiency in scripting languages, Python, Linux for test automation, data collection and analysis.
• Knowledge of DC-DC converters, open compute power architecture, SoC power architecture, and component-/tray-/rack-level power management and optimization.
• Understanding of power testing methodologies and expertise in bench level Hardware (HW) validation using test equipment.

Responsibilities

• Define, execute and document electrical characterization, validation and qualification of on-board system-level power distribution network, covering from the power converter design to ASIC power integrity validation.
• Work with minimal guidance to troubleshoot and root cause electrical component level defects and design issues.
• Support design engineers with debug, component validation, and failure analysis of released products.
• Develop test procedures for general qualification and targeted testing of Devices Under Test (DUTs) using automated/scripted tests as part of a larger automation suite.
• Collect and analyze aggregated data to enable data driven engineering decisions during HW R&D, report on findings, reduce test data, and investigate test outcomes thoroughly down to a hardware interface or component level.

Skills

Python

Linux

Test automation

Data analysis

Education

Bachelor's degree in EE/CE/Physics or related field

Master's or PhD in EE/CE/Physics

Tools

Oscilloscopes

Programmable power supplies

Spectrum analyzers

DMMs

Function generators

Job description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
• 4 years of experience working in a power electronics technical environment, or 3 years of experience with an advanced degree.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field.
• 1 year of experience in technical leadership.
• Experience in power measurement equipment such as oscilloscopes, programmable power supplies, spectrum analyzers, DMMs and function generators.
• Proficiency in scripting languages, Python, Linux for test automation, data collection and analysis.
• Knowledge of one or more of the following: DC-DC converters, open compute power architecture, SoC power architecture, and component-/tray-/rack-level power management and optimization.
• Understanding of power testing methodologies and expertise in bench level Hardware (HW) validation using test equipment.

About the job:

As a Senior Hardware Test Engineer, you will be supporting a team of hardware board and power designers who are responsible for prototype bring-up, validation, qualification, and failure analysis of server-related technologies such as Central Processing Unit (CPU), Double Data Rate (DDR) memory, storages, onboard power and high-speed interconnects. You will also be responsible for liaison between Hardware (HW) engineering teams and the lab team to ensure lab resources are accounted for and to ensure we are 'lab-ready' for new products entering the Research and Development (R&D) labs or sustaining efforts.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $159000 - $230000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities:

• Define, execute and document electrical characterization, validation and qualification of on-board system-level power distribution network, covering from the power converter design to Application-Specific Integrated Circuit (ASIC) power integrity validation.
• Work with minimal guidance to troubleshoot and root cause electrical component level defects and design issues.
• Support design engineers with debug, component validation, and failure analysis of released products.
• Develop test procedures for general qualification and targeted testing of Devices Under Test (DUTs) using automated/scripted tests as part of a larger automation suite.
• Collect and analyze aggregated data to enable data driven engineering decisions during HW R&D, report on findings, reduce test data, and investigate test outcomes thoroughly down to a hardware interface or component level.