Senior GPU System Architect: Multi-GPU AI/HPC Scale-Out

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 184,000 - 357,000; Full time

Benefits offered by this job

Equity compensation

Benefits package

Hybrid work model

Job summary

NVIDIA Corporation seeks a GPU System Architect to design multi-GPU scale-up and scale-out systems for AI and HPC datacenters. You will architect architectures that tightly couple GPU compute, high-bandwidth memory, and interconnects to deliver leading AI performance and resilience.

The ideal candidate combines deep hands-on system-level fabric experience with practical hardware-software co-design across compute, memory and communication layers, collaborating across silicon, packaging, board,

Qualifications

• BS/MS/PhD in Electrical Engineering or Computer Engineering (or equivalent).
• 8+ years in system design and/or ASIC/SoC architecture for GPU/CPU or networking products.
• Deep knowledge of NVLink, Ethernet, InfiniBand, CXL and PCIe protocols.

Responsibilities

• Architect multi-GPU system topologies for scale-up and scale-out AI/HPC workloads.
• Define and evaluate high-speed interconnect architectures (NVLink, PCIe, Ethernet).
• Collaborate with ASIC, compiler, library and software teams for hardware-software co-design.
• Model systems, run simulations, and perform bottleneck analyses to guide design trade-offs.
• Assist interposer, package, PCB and switch co-design for dense multi-die, multi-package racks.

Skills

System-level design

Python

SystemC

Collaboration

Education

BS/MS/PhD in Electrical/Computer Engineering

Tools

Verilog

SystemC

Job description

NVIDIA Corporation seeks a GPU System Architect to design multi-GPU scale-up and scale-out systems for AI and HPC datacenters. You will architect architectures that tightly couple GPU compute, high-bandwidth memory, and interconnects to deliver leading AI performance and resilience.

The ideal candidate combines deep hands-on system-level fabric experience with practical hardware-software co-design across compute, memory and communication layers, collaborating across silicon, packaging, board,