Senior GPU Power Architect for AI & HPC

NVIDIA; Santa Clara (CA); Presencial; USD 168.000 - 311.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Equity compensation

Benefits package

Descripción de la vacante

NVIDIA's Applied Power Architecture team seeks a Senior Applied Power Architect – GPU to drive energy-efficient GPU/SoC designs for AI, automotive, and mobile products. You will lead power integrity initiatives, PDN design efforts, and cross-disciplinary collaboration to optimize performance within thermal/PV constraints.

The role requires 6+ years in low-power architecture, strong PDN and power modeling skills, and experience with Python data tools. On-site in Santa Clara, US.

Formación

• MSEE/MSCE, preferably PhD, or equivalent with specialization in low-power processor architectures.
• 6+ years of experience in energy-efficient system design and power modeling.
• Background in PDN design and electrical issues such as Di/Dt, undershoot/overshoot, IR/EM helpful.
• Exposure to Python and data analysis packages like Pandas, NumPy; PyTorch is a plus.

Responsabilidades

• Invent methodologies and techniques to address electrical/speed/power challenges for next-gen AI architectures.
• Drive power management initiatives to optimize power efficiency and performance under constraints.
• Analyze process characteristics and V-F tradeoffs, considering VT choices on power and performance.
• Investigate multi-die technologies and propose solutions for packaging, interconnect, and thermal challenges.
• Collaborate with ASIC designers, Power Integrity, Packaging, and Product engineers to implement solutions.

Conocimientos

Power integrity

PDN design

Power/thermal analysis

Python

Data analysis (Pandas/NumPy)

Team collaboration

Educación

MSEE/MSCE or PhD

Herramientas

PyTorch

Pandas

NumPy

Scope/DAQ

Descripción del empleo

NVIDIA's Applied Power Architecture team seeks a Senior Applied Power Architect – GPU to drive energy-efficient GPU/SoC designs for AI, automotive, and mobile products. You will lead power integrity initiatives, PDN design efforts, and cross-disciplinary collaboration to optimize performance within thermal/PV constraints.

The role requires 6+ years in low-power architecture, strong PDN and power modeling skills, and experience with Python data tools. On-site in Santa Clara, US.