Senior FPGA Verification Engineer

Anduril-1; Broomfield (CO); On-site; USD 165,000 - 218,000; Full time

Job summary

Anduril Industries is seeking a Senior FPGA Verification Engineer to design and verify new product lines. You will work with a cross-disciplinary team to define, mature, and test prototypes through ground and flight testing, advancing them into production.

The role emphasizes architecture of verification environments, testplan creation, and leadership across project verification teams, with an expectation for deep expertise in HDL, SystemVerilog, and FPGA/ASIC verification methodologies.

Qualifications

• Bachelor's in Electrical Engineering, Computer Engineering or related field.
• 8+ years HDL firmware development for FPGA devices.
• Experience with HDL simulation RTL designs using VHDL/Verilog.
• Proven ability to design and execute verification testbenches for RTL blocks (VHDL/SystemVerilog).
• Experience with chip-level verification methodologies: constrained-random testing, functional coverage, assertion-based verification (SystemVerilog).
• Experience with Git or SVN for source control and collaboration.
• Eligible to obtain and maintain an active U.S. Secret security clearance.

Responsibilities

• Define verification environment architecture and design using SystemVerilog and UVM/OVM.
• Create test plans, test cases, code coverage and functional coverage tracking.
• Develop testbenches for RTL blocks using VHDL/SystemVerilog.
• Recommend new tools and practices for continuous improvement of FPGA/ASIC flow.
• Contribute to engineering estimates for new programs.
• Provide technical leadership for project verification teams and plan activities.

Skills

HDL Firmware

VHDL

Verilog

SystemVerilog

Testbenches

RTL Verification

Git

SVN

Security Clearance

Education

Bachelors in EE

Tools

QuestaSim

Synplify

Quartus

Vivado

Job description

Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century’s most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril’s family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years.

ABOUT THE TEAM

The Anduril Imaging team developsstate-of-the-artimaging systems across both hardware and software, deployed to tackle the most significant security challenges of America and its allies.The team is heavily involved inutilizingcomputer vision, perception, electro-optical, infrared, and sensor data to give our war fighters and allies an advantage.

ABOUT THE JOB

The Imaging team is seeking a Senior FPGA Verification Engineer to help design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products.

WHAT YOU’LL DO

• Verification environment architecture and design usingtools likeSystemVerilogorOVM/UVM
• Creation of written test plan, testcases, code coverage tracking, and functional coverage tracking
• Testbench development for the verification of RTL blocks using VHDL orSystemVerilog
• Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
• Contribute to engineering estimates for new program pursuits.
• Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status

REQUIRED QUALIFICATIONS

• ABachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typicallyrequired.
• 8+ years of experience developing HDL firmware for FPGA devices
• Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
• experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
• Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/orSystemVerilog.
• experience applying chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog)
• Experience using revision control systems such as Git or Subversion to manage source code, collaborate across engineering teams, andmaintainconfiguration integrity.
• Eligible to obtain andmaintainan active U.S. Secret security clearance

PREFERRED QUALIFICATIONS

• Experience with ASIC/FPGA lab validation and debug using standard lab equipment, along with familiarity with DFT, manufacturability, and production test concepts.
• Proficiencywith Unix/Linux environments,scriptingor software development (C, C++, Python, Perl, or shell), and industry-standard ASIC/FPGA simulation and synthesis tools such asQuestaSim,Synplify, Quartus, orVivado.

US Salary Range

$165,000 - $218,000 USD

The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are included in the majority of full time offers; and are considered part of Anduril's total compensation package. Additionally, Anduril offers top-tier benefits for full-time employees, including:

At Anduril, we invest in our people. Our comprehensive, competitive benefits package (available at little to no cost to employees) ensures you’re supported in health, recovery, and whatever comes next. For more information, Explore Our Benefits .

Voluntary Self-Identification

For government reporting purposes, we ask candidates to respond to the below self-identification survey.Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiringprocess or thereafter. Any information that you do provide will be recorded and maintained in aconfidential file.

As set forth in Anduril Industries’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.

If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection.As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measurethe effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. Classification of protected categoriesis as follows:

A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service-connected disability.

A "recently separated veteran" means any veteran during the three-year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service.

An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.S. military, ground, naval or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense.

An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.