Senior FPGA & Firmware Engineer - SDR

Axon Enterprise; Scottsdale (AZ); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

401k matching

Paid time off

Parental leave

Fitness programs

Mental wellness

Snacks in office

Job summary

Axon is seeking a Senior FPGA/RTL Design Engineer to own the FPGA realization of DSP for a software-defined radio across the Mesh & Opportunistic Networking team.

You will model in MATLAB/Simulink, generate RTL from Simulink, and implement designs in Vivado, collaborating with firmware, RF, and product teams to deliver high-performance OFDM modem blocks.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering.
• 6+ years FPGA/RTL design from architecture to bring-up.
• Proficient in VHDL/Verilog/SystemVerilog with testability.
• Strong experience with Xilinx Vivado and timing constraints.
• Matlab/Simulink modeling for algorithms; model-based design.

Responsibilities

• Research, model, and implement SDR and digital comms algorithms (OFDM, FFT/IFFT, MIMO, LDPC).
• Generate RTL from Simulink via HDL Coder; write VHDL/Verilog as needed.
• Works through Vivado flow: synthesis, place-and-route, timing closure.
• Architect AXI4/AXI4-Stream interfaces, DMA, FIFOs; CDC handling.
• Verify with HDL simulations, testbenches, and regression suites.
• Collaborate across RF, firmware, and software to integrate modem.

Skills

RTL design

VHDL/Verilog

MATLAB/Simulink

Vivado toolchain

AXI4/AXI4-Stream

HDL Coder

FPGA bring-up

DSP fundamentals

Digital communications

Documentation/Presentation

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering

Tools

Vivado

HDL Coder

MATLAB/Simulink

Job description

At Axon, we’re on a mission to Protect Life. We’re explorers, pursuing society’s most critical safety and justice issues with our ecosystem of devices and cloud software. Like our products, we work better together. We connect with candor and care, seeking out diverse perspectives from our customers, communities and each other.
Life at Axon is fast-paced, challenging and meaningful. Here, you’ll take ownership and drive real change. Constantly grow as you work hard for a mission that matters at a company where you matter.

Your Impact

As a Senior member of the Mesh & Opportunistic Networking team, you will own the FPGA realization of the digital signal processing that powers our software‑defined radio. You will take wireless communication algorithms from concept through behavioral modeling in MATLAB/Simulink, into synthesizable RTL, and onto silicon — meeting aggressive timing, resource, and power targets on a Zynq UltraScale+ MPSoC. You will apply deep expertise in DSP, digital communications, and FPGA design to deliver a robust, high‑performance OFDM modem, and you will collaborate closely with firmware, systems, RF, and product engineering to bring the full radio together. You will mentor junior engineers, raise the technical bar for our model‑based design and verification practices, and continue to grow your own technical leadership. Join a passionate engineering team dedicated to overcoming complex challenges, and help deliver technologies that positively impact Law Enforcement, Public Safety, and their surrounding communities.

Location - This role is based out of our Boston or Scottsdale offices and follows a hybrid schedule. We rely on in‑person collaboration and ask that team members work onsite Tuesdays through Fridays, with the flexibility to work remotely on Mondays, unless there is an approved workplace accommodation. We believe that connection fuels innovation, and our in‑office culture is designed to foster meaningful teamwork, mentorship, and shared success.

What You’ll Do

• Research, model, and implement industry‑leading SDR and digital communications algorithms — OFDM modulation/demodulation, FFT/IFFT, channel estimation and equalization, synchronization, MIMO, and forward error correction (LDPC) — for products in our mesh and connected‑device portfolio
• Develop floating‑ and fixed‑point behavioral reference models in MATLAB/Simulink, make quantization and architecture trade‑offs, and validate algorithm performance against link‑budget and BER/PER requirements
• Generate and integrate RTL from Simulink using HDL Coder, and author hand‑written VHDL/Verilog where custom or performance‑critical logic is required
• Implement designs in Vivado through the full flow — synthesis, place‑and‑route, and timing closure — authoring and refining XDC timing and physical constraints to meet timing on high‑utilization, multi‑clock designs
• Architect and implement on‑chip interfaces and data movement: AXI4 / AXI4‑Stream, DMA, register interfaces, FIFOs, and robust clock‑domain‑crossing (CDC) logic
• Build and maintain rigorous verification: Simulink/HDL co‑simulation, bit‑true comparison against the reference model, RTL testbenches, and automated regression suites
• Integrate the modem with the RF transceiver front end (e.g., ADRV9001) and with the ARM application cores, partitioning functionality across the heterogeneous SoC
• Collaborate with electrical engineering on concerns that span the FPGA/RF boundary — power and thermal budgets, generation of test and characterization waveforms, and digital pre‑distortion (DPD) for power amplifier linearization
• Bring up, characterize, and debug the radio on hardware using oscilloscopes, logic/protocol analyzers, spectrum and vector signal analyzers, and on‑chip debug (ILA/VIO)
• Collaborate with firmware engineering to define and debug the hardware/software interface, register maps, and data pipelines
• Evaluate and document design outcomes, timing/resource reports, and verification results, and present findings to the design team for review and further action
• Optimize performance, area, and power through micro‑architecture refinement, pipelining, and resource sharing, guided by simulation and hardware measurement
• Develop and maintain design documentation, interface control documents, and release artifacts needed for product integration
• Mentor junior engineers and contribute to team knowledge sharing and best practices in model‑based design and FPGA development

What You’ll Bring

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a similar engineering discipline
• 6+ years of industry FPGA/RTL design experience taking digital logic from architecture through synthesis, timing closure, and hardware bring‑up
• Highly proficient in RTL design with VHDL and/or Verilog/SystemVerilog, including synthesizable coding practices and design for testability
• Strong hands‑on proficiency with the Xilinx/AMD Vivado toolchain — synthesis, implementation, timing constraints (XDC), and timing closure on complex, high‑utilization designs
• Demonstrated experience with MATLAB and Simulink for algorithm modeling, and with model‑based design workflows
• Solid foundation in digital signal processing and digital communications: sampling, filtering, FFTs, modulation/demodulation, and an understanding of wireless link fundamentals
• Experience with fixed‑point arithmetic, quantization analysis, and the trade‑offs between numerical precision, area, and performance
• Proficient with on‑chip interconnect and interfaces — AXI4/AXI4‑Stream, DMA, memory interfaces — and with clock‑domain‑crossing design
• Strong RTL verification skills: testbench development, HDL simulation, and verifying RTL against a golden/reference model
• Strong hands‑on proficiency with FPGA and system bring‑up and debug using laboratory tools: oscilloscope, logic/protocol analyzers, spectrum/signal analyzers, and integrated logic analyzers (ILA/VIO)
• Proficient with modern AI‑assisted development tools and coding assistants (e.g., Claude Code, Cursor, GitHub Copilot), and able to apply them effectively and responsibly to accelerate design, verification, scripting, documentation, and debug
• Independent contributor capable of developing complex designs within cross‑functional and geographically diverse engineering teams
• Strong proficiency in documentation, analysis, and presentation tools, including Word, Excel, and PowerPoint

Preferred Qualifications

• Master’s or PhD in Electrical Engineering, Communications, or Signal Processing
• Production experience with HDL Coder (or equivalent high‑level synthesis / model‑to‑RTL) workflows, including code generation, optimization, and verification of generated RTL
• Hands‑on experience implementing OFDM modems and/or channel coding (LDPC, Turbo, convolutional/Viterbi), MIMO, channel estimation, and synchronization in hardware
• Experience designing on Zynq / Zynq UltraScale+ MPSoC or other heterogeneous SoC/FPGA platforms, including hardware/software partitioning with embedded processors
• Experience integrating wideband RF transceivers (e.g., Analog Devices ADRV9001/ADRV9002) or other SDR front ends, and implementing or supporting RF impairment correction such as digital pre‑distortion (DPD)
• Familiarity with software‑defined radio platforms and frameworks (e.g., GNU Radio) and over‑the‑air testing
• Experience with version control (Git) and CI for HDL/model‑based design
• Experience applying AI coding assistants to FPGA/HDL workflows — RTL generation and review, testbench creation, constraint and timing analysis, MATLAB/Simulink and Tcl scripting, and design documentation — with sound judgment about where generated output must be verified

Benefits that Benefit You

• Competitive salary and 401k with employer match
• Discretionary paid time off
• Paid parental leave for all
• Fitness Programs
• Emotional & Mental Wellness support
• And yes, we have snacks in our offices

Don’t meet every single requirement? That's ok. At Axon, we Aim Far. We think big with a long‑term view because we want to reinvent the world to be a safer, better place. We are also committed to building diverse teams that reflect the communities we serve.

Studies have shown that women and people of color are less likely to apply to jobs unless they check every box in the job description. If you’re excited about this role and our mission to Protect Life but your experience doesn’t align perfectly with every qualification listed here, we encourage you to apply anyways. You may be just the right candidate for this or other roles.

The above job description is not intended as, nor should it be construed as, exhaustive of all duties, responsibilities, skills, efforts, or working conditions associated with this job. The job description may change or be supplemented at any time in accordance with business needs and conditions.

Some roles may also require legal eligibility to work in a firearms environment.

Axon’s mission is to Protect Life and is committed to the well‑being and safety of its employees as well as Axon’s impact on the environment. All Axon employees must be aware of and committed to the appropriate environmental, health, and safety regulations, policies, and procedures. Axon employees are empowered to report safety concerns as they arise and activities potentially impacting the environment.

We are an equal opportunity employer that promotes justice, advances equity and values diversity and fosters inclusion. We’re committed to hiring the best talent — regardless of race, creed, color, ancestry, religion, sex (including pregnancy), national origin, sexual orientation, age, citizenship status, marital status, disability, gender identity, genetic information, veteran status, or any other characteristic protected by applicable laws, regulations and ordinances — and empowering all of our employees so they can do their best work. If you have a disability or special need that requires assistance or accommodation during the application or the recruiting process, please email [e-mail]. Please note that this email address is for accommodation purposes only. Axon will not respond to inquiries for other purposes.

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