Senior Engineer II - CAD (Physical Verification)

Microchip Technology; United States; On-site; USD 120,000 - 170,000; Full time

Job summary

Microchip Technology Inc's CAD group is seeking a seasoned professional to develop and support physical verification flows for multiple PDKs across process technologies, focusing on back-end verification. The candidate will work with Calibre, Pegasus, and related tools to streamline regression tests and improve reliability.

The role requires 7.5–10 years of experience, strong SVRF/TVF knowledge, and proficiency in Tcl/Tk, Perl, and Python.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 7.5–10 years of experience in physical verification development and support.
• Deep knowledge of Calibre DesignRev scripting.
• Fluent with SVRF and TVF.
• Debug PV issues with RVE, Vue or other EDA visualizers.
• Proficient in Tcl/Tk, Perl, Python and other scripting languages.
• Strong understanding of layout rules, foundry rules, and design for manufacturability.
• Experience with Calibre/Pegasus/Hercules syntax and semantics.
• Experience with Cadence Virtuoso and/or CalibreDRV.
• Excellent verbal and written communication and interpersonal skills.

Responsibilities

• Develop physical verification regression test cases to QA physical verification decks.
• Support Layout and Design engineers with physical verification activities using verification tools such as Siemens Calibre, Cadence Pegasus, or Synopsys Hercules.
• Utilise Knowledge of advanced EDA methods to support ESD, ERC, Voltage-Aware DRC, via doubling methodologies, etc.
• Work with Technology Development and Device Engineering to develop DRC rules, additional devices, and design for manufacturability checks.
• Develop rule decks as needed to support flow.
• Verify and enhance foundry rule decks.
• Support remote sites worldwide with layout verification activities.
• Support debug of physical verification issues.
• Work as a member of team to develop flows to improve quality and reliability of devices.

Skills

EDA scripting

SVRF

TVF

Tcl/Tk

Python

Debug PV issues

Communication

Team collaboration

Foundry rules understanding

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering (Preferred)

Tools

Calibre

Pegasus

Hercules

CalibreDRV

Cadence Virtuoso

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

The CAD group at Microchip offers global support for multiple technology nodes and tools used in product development providing innovative solutions for the design community. The candidate will focus on flow development and support for back end physical verification. If you have a solid software background and are interested in supporting semiconductor chip design, this maybe the job for you.

Expertise using Siemens Calibre and/or Cadence Pegasus DRC, LVS and PERC tools is paramount. Candidate should not only know how to run the tools and debug results, but also have strengths in developing the verification run decks and in automating flow/procedures.

An overall strong understanding in both the digital and analog sides of design is important to be effective, since development and support work will span a variety of design styles. Additionally, both circuit/electrical and layout/physical knowledge is important.

The candidate will:

• Develop physical verification regression test cases to QA physical verification decks
• Support Layout and Design engineers with physical verification activities using verification tools such as Siemens Calibre, Cadence Pegasus, or Synopsys Hercules
• Utilise Knowledge of advanced EDA methods to support ESD, ERC, Voltage-Aware DRC, via doubling methodologies, etc.
• Work with Technology Development and Device Engineering to develop DRC rules, additional devices, and design for manufacturability checks
• Develop rule decks as needed to support flow
• Verify and enhance foundry rule decks
• Support remote sites worldwide with layout verification activities
• Support debug of physical verification issues
• Work as a member of team to develop flows to improve quality and reliability of devices

The tasks this candidate will be assigned depends on their experience. There are several areas in which we are shorthanded. Potential task assignments would include:

• Building of regression test cases for several PDKs of various process technologies
• Supporting 4nm to 600nm PDKs from TSMC, Global Foundries, Vanguard, Dongbu, Magnachip, etc.
• Calibre/Pegasus PERC - several PDKs still require PERC setup.

Requirements/Qualifications:

• Bachelors in Electrical Engineering or related field with 7.5 to 10 years experience developing and supporting physical verification activities
• In depth knowledge of Calibre DesignRev scripting
• Fluent with SVRF and TVF
• Accomplished at debugging PV issues with RVE, Vue or other EDA visualizer
• Familiar with customizing Calibre Interactive Skilled with Tcl/Tk, Perl, Python, and other programming languages, inside and outside of EDA tools
• Solid knowledge of layout rules and concepts, device identification concepts, and foundry rules
• Strong knowledge of Design for Manufacturing solutions affecting quality, reliability, and yield of designs
• Prefer extensive knowledge of Calibre/Pegasus/Hercules syntax and semantics, or similar layout verification tool
• Strong knowledge of Cadence Virtuoso and/or CalibreDRV
• Excellent verbal and written communication and interpersonal skills

Preferred:

• Masters in Electrical Engineering or related field
• Prefer Extraction, Reliability and Dynamic Noise related knowledge

Travel Time:

0% - 25%

Physical Attributes:

Feeling, Handling, Hearing, Seeing, Works Alone, Works Around Others

Physical Requirements:

80% sitting, 10% standing, 10% walking, 100% inside

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment