Senior Digital Design Engineer, Air Dominance and Strike

Anduril-1; Costa Mesa (CA); On-site; USD 166,000 - 220,000; Full time

Benefits offered by this job

Equity grants

Top-tier benefits

Job summary

Anduril Industries in Costa Mesa, CA is seeking a Senior FPGA Design Engineer to design and integrate RTL for FPGA/SoC platforms used in high-performance embedded avionics and mission-critical hardware.

You will own designs from architecture through timing closure, run simulations, support lab bring-up, and collaborate across hardware, software, and systems teams; U.S. Secret clearance eligibility required.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of FPGA, ASIC, or closely related digital design experience.
• Proficiency in VHDL and/or Verilog/SystemVerilog.
• Hands-on experience with simulation, synthesis, implementation, and timing closure on modern FPGA platforms.
• Hands-on debug experience in simulation and on hardware.
• Strong digital design fundamentals and CDC awareness.
• Proficiency with Linux-based development environments, Git-based workflows, and Tcl and/or Python scripting.
• Eligible to obtain and maintain an active U.S. Secret security clearance.

Responsibilities

• Design and implement RTL in VHDL, Verilog, or SystemVerilog for FPGA/SoC systems.
• Translate requirements into microarchitecture, interfaces, and plans.
• Own FPGA designs through architecture, timing closure, and lab debugging.
• Develop and execute simulation, synthesis, and implementation flows including timing/resource closure.
• Debug functional and timing issues in simulation and on hardware.
• Support board bring-up, lab validation, and system integration.
• Collaborate with hardware, software, systems, and verification engineers to deliver solutions.
• Participate in design and code reviews and documentation.
• Contribute to reusable design practices and development workflows.
• Support rapid prototyping while maintaining engineering rigor.

Skills

FPGA design

Verilog/SystemVerilog

VHDL

Linux development

Git workflows

Python scripting

strong communication

Education

Bachelor's degree in Electrical Engineering or related

Tools

AMD/Xilinx/Lattice tools

Vitis or similar tooling

Job description

Senior Digital Design Engineer, Air Dominance and Strike

Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century’s most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril’s family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years.

ABOUT THE TEAM

The Air Dominance and Strike (AD&S) Electrical Engineering Team develops high-reliability avionics, embedded processing, and power systems for Group 5 air vehicles and missile platforms. Working across hardware, software, and mission autonomy, the team delivers flight-critical electronics, PCB assemblies, and FPGA-based processing architectures for Anduril's next-generation autonomous air platforms. AD&S Electrical Engineers drive end-to-end development, from system architecture and circuit design through verification, integration, and flight test, delivering mission-ready systems that meet demanding performance, reliability, and survivability requirements.

ABOUT THE JOB

We are looking for an Senior FPGA Design Engineer to join our team in Costa Mesa, CA. In this role, you will design and integrate RTL for FPGA and SoC platforms used in high-performance embedded systems, avionics, and mission-critical hardware. You will work across the full development cycle, from requirements and microarchitecture through RTL implementation, simulation, synthesis, timing closure, lab bring-up, and system integration.

We welcome candidates from a range of complex digital hardware environments.

WHAT YOU'LL DO

• Design and implement RTL in VHDL, Verilog, orSystemVerilogfor FPGA and SoC-based systems.
• Translate system and hardware requirements into microarchitecture, interface definitions, and implementation plans.
• Own FPGA designs or major functional blocks from architecture through integration, timing closure, and lab debug.
• Develop and execute simulation, synthesis, and implementation flows, including timing and resource closure.
• Debug functional, timing, and integration issues in simulation and on hardware.
• Support board bring-up, lab validation, and system integration on target platforms.
• Collaborate with hardware, embedded software, systems, and verification engineers to deliver complete solutions.
• Participate in design reviews, code reviews, and technical documentation.
• Contribute to reusable design practices, coding standards, and development workflows.
• Support rapid prototyping whilemaintainingthe engineering rigor required for production hardware.

REQUIRED QUALIFICATIONS

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of FPGA, ASIC, or closely related digital design experience.
• Proficiencyin VHDL and/or Verilog/SystemVerilog.
• Hands-on experience with simulation, synthesis, implementation, and timing closure on modern FPGA platforms.
• Hands-on debug experience in simulation and on hardware.
• Strong digital design fundamentals, including clocking, resets, state machines, CDC awareness, and interface design.
• Proficiencywith Linux-based development environments, Git-based workflows, andTcland/or Python scripting.
• Strong written and verbal communication skills.
• Eligible to obtain andmaintainan active U.S. Secret security clearance.

PREFERRED QUALIFICATIONS

• 12+ years of FPGA development experience.
• Experience owning a major functional block, subsystem, or full FPGA design from concept through integration.
• Familiarity with AMD (Xilinx), Intel/Altera, or Lattice FPGA development environments.
• Experience with embedded systems and hardware/software co-design, including AMD (Xilinx) Vitis or similar tooling.
• Familiarity with common high-speed or embedded interfaces such as Ethernet, PCIe, JESD204, SPI, I2C, UART, CAN, or MIL-STD-1553.
• Familiarity with DO-254 or similar military or safety-critical development standards.
• Experience building or improving reusable IP, verification infrastructure, CI/CD flows, or team workflows.
• Familiarity with modern build and development tooling such as Jira, automated regression infrastructure, and reproducible build environments.

US Salary Range

$166,000 - $220,000 USD

The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are included in the majority of full time offers; and are considered part of Anduril's total compensation package. Additionally, Anduril offers top-tier benefits for full-time employees, including:

At Anduril, we invest in our people. Our comprehensive, competitive benefits package (available at little to no cost to employees) ensures you’re supported in health, recovery, and whatever comes next. For more information, Explore Our Benefits.