Senior DFX Engineer

Ericsson; Austin (TX); Hybrid; USD 140,000 - 190,000; Full time

Job summary

Ericsson Austin is seeking a Senior DFX Engineer to lead silicon lifecycle management across multiple ASIC programs. You will design, verify, and implement DFT/SLM capabilities, extend in-field testing and telemetry, and partner with test, physical design, and CAD teams to push innovative DFX flows.

You will mentor engineers, work with global teams, and apply AI to automate workflows and diagnostics, improving reliability and time-to-market for complex SOCs.

Qualifications

• 5+ years of experience in SOC/IP/ASIC design with emphasis around DFX
• Experience with SOC level DFT planning, architecture, and execution
• Familiarity with IEEE 1149.1, 1687, and 1838 is a plus
• Good focus on automation & infrastructure to enable efficient execution pipeline within DFX function
• Experience applying AI/ML to engineering workflows or a drive to build it into daily execution

Responsibilities

• Strengthen a world-class DFX & SLM group and its role as the technical authority for silicon lifecycle management
• Strategize, architect, plan, design/implement & verify DFT and SLM capability across multiple ASIC programs
• Extend our silicon lifecycle capability in the field: in-system test, silicon telemetry, monitoring, diagnostics, and repair
• Partner with Test Team to define overall Test Strategy
• Partner with Physical Design teams (IP & SOC) to develop complex SOCs
• Work closely with EDA Vendors, ASIC partners & CAD team to define next generation DFT/SLM flows and methodology
• Apply AI as a first-class tool in daily execution: automating flows, accelerating debug and triage
• Mentor & coach junior engineers within the team and helping them achieve their goals
• Collaborate with cross site / geography teams to help establish great working relationship and deal very efficiently with deliverables across teams

Skills

DFX expertise

Automation & infra

AI/ML in workflows

Post-silicon debugging

Education

BSEE

Tools

IEEE 1149.1

IEEE 1687

IEEE 1838

JTAG / iJTAG

BIST / ATPG

Job description

Grow with us

Senior DFX Engineer, Austin, Texas.

Hybrid, on-site work schedule

This is not a remote work opportunity.

About this opportunity

The Ericsson Radio and Baseband Products have our ASICs as their backbone, and our challenge is to design and deliver those so that our technology leadership position in the market accelerates. Our ASICs are challenging when considering the overall combination of Size/complexity, Test Quality & Reliability, Power, Performance targets, advanced process node technology, multi-die integration, and pushing the design methodology on an ongoing basis. We are looking for a DFX Engineer to join our established & very experienced DFX & SLM team (Silicon Lifecycle Solutions), the technical authority for DFX and Silicon Lifecycle Management across Ericsson Silicon. With production silicon in the field and multiple ASIC programs in active development, the team owns DFX/SLM from chip specification through tape-out sign-off to years of in-field operation. The role covers all aspects of DFX and SLM (Architecture, Design, Verification, Methodology, Production Test, Silicon Debug, In-field Test & Telemetry). It includes working closely with other functions within Austin and in Sweden, and with our ASIC and EDA partners, as the design takes shape at the IP, SOC, and system level to ensure that the final ASIC achieves the program goals.

What You Will Do

• Strengthen a world-class DFX & SLM group and its role as the technical authority for silicon lifecycle management
• Strategize, architect, plan, design/implement & verify DFT and SLM capability across multiple ASIC programs, from chip specification to tape-out sign-off
• Extend our silicon lifecycle capability in the field: in-system test, silicon telemetry, monitoring, diagnostics, and repair
• Partner with Test Team to define overall Test Strategy
• Partner with Physical Design teams (IP & SOC) to develop complex SOCs
• Work closely with EDA Vendors, ASIC partners & CAD team to define next generation DFT/SLM flows and methodology with latest & greatest features
• Apply AI as a first-class tool in daily execution: automating flows, accelerating debug and triage, and extracting insight from silicon and system telemetry
• Mentor & coach junior engineers within the team and helping them achieve their goals
• Collaborate with cross site / geography teams to help establish great working relationship and deal very efficiently with deliverables across teams

Join our Team

You will bring

• 5+ years of experience working in SOC/IP/ASIC design team with an emphasis around DFX (DFT/DFD/DFM). Experience on DFX Verification specifically (Verification of features like: Memory BIST, JTAG, Boundary Scan, In-field Tests, Custom IP Test Interface etc.) would be of great interest for this role.
• Minimum Education: BSEE
• Must have working knowledge about DFX standards and practices, ATPG, Scan, JTAG, iJTAG, BIST, including trade-offs between test quality, test time, efficiency, and their impact to overall design implementation.
• Experience with SOC level DFT planning, architecture, and execution.
• Exposure to Silicon Lifecycle Management: in-field/in-system test, telemetry-driven monitoring and diagnostics, and RAS concepts. Familiarity with IEEE 1149.1, 1687, and 1838 is a plus.
• Good focus on automation & infrastructure to enable efficient execution pipeline within DFX function.
• Experience applying AI/ML to engineering workflows (debug, triage, data analysis, flow automation), or a demonstrated drive to build it into daily execution.
• Experience with post silicon debug, yield bring up, test-time and pattern delivery while working closely with Test & Product Engineering teams for long term strategic improvements.
• Continuous drive to improve flows, methodology and architecture for enabling scalability of the overall team in years to come.
• Understanding of Physical design implementation flows and methods to enable a smooth integration of DFT in the design with efficient and quality hand offs.

This role reports to the DFX & SLM Engineering Lead

Why join Ericsson?

At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.

Ericsson uses a merit-based hiring approach that values people with different experiences, perspectives and skillsets. We truly believe this approach drives innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity employer, learn more.

If you need assistance or to request an accommodation due to a disability, please contact Ericsson at [e-mail].

Primary country and city: USA, Austin Texas

Job details: Developer

Compensation And Benefits At Ericsson

At Ericsson, we know that our people are the key to our success. We offer a competitive package to help with your individual needs and goals.

Your Pay

The salary range for this position is dependent on various factors including, but not limited to, location, and the candidate’s combination of job-related knowledge, qualifications, skills, education, training, and experience.

Short-Term Variable Compensation Plan:

Your pay also includes the opportunity for an annual bonus. Actual bonus payouts are based on performance of the business against the unit’s objectives, individual performance, and the individual bonus target. Certain eligibility and pro-ration rules apply.

Your Health

Ericsson offers excellent health benefits including the choice of three medical plan options and a dental plan option that allow an employee to select the level of coverage that suits their needs. Employees will receive company credits in an amount equal to the cost that Ericsson pays toward the cost of their medical and dental premiums for themselves and eligible covered dependents.

Your Financial Security

We invest in both your short and long-term financial wellbeing. The Ericsson US 401(k) Plan offers an automatic 3% company contribution and Ericsson match $1 for every $1 you put into the 401(k) Plan on the first 3% of your eligible pay, plus 50 cents on every $1 on the next 2% of eligible pay. When you contribute at least 5% of eligible pay, you are receiving Ericsson’s full matching contributions of 4%. Matching and company automatic contributions stop when your total eligible pay for the year reaches the IRS limits. Employees will also receive company credits in an amount equal to the cost of basic life insurance and basic accidental death and dismemberment coverage, as well as short-term and long-term disability coverage. Employees also have the option to participate in Ericsson’s Stock Purchase Plan.

Your Time

Your work-life balance is important to us. New employees are provided a minimum of 15 days of accrued vacation, up to 3 personal days per year, 11 annual holidays, 8 hours of volunteer time, and 80 hours of sick time annually. Please note paid time off is pro-rated based on the employee’s start date. Furthermore, Ericsson provides up to 16 weeks of paid maternity leave and 6 weeks of parental or adoption leave at 100% of pay.

Additional Benefits

Ericsson offers many other company-paid benefits such as financial wellness programs, educational assistance, matching gifts, and recognition programs.

DISCLAIMER:

The above statements are intended to describe the general nature and level of work being performed by employees in this position. They are not an exhaustive list of all responsibilities, duties and skills required for this position, and you may be required to perform additional job tasks as assigned.