Senior DFT Architect for Edge AI SoCs

Socket.dev; United States; Remote; USD 200,000 - 250,000; Full time

Job summary

EnCharge AI is seeking a Lead DFT Engineer to architect test strategies for edge-to-cloud chips, balancing high-performance processing with power efficiency in remote environments.

You will lead DFT architecture, IST/POST methods, and oversee ATPG and MBIST efforts, collaborating with Design, Physical Design, and Yield teams to achieve high test coverage with minimal area and power impact.

Qualifications

• 12+ years in DFT with at least 2 years in a leadership or principal role.
• Bachelor’s degree in a related field.
• Mastery of industry-standard DFT tools (Synopsys TestMAX, Tessent, Cadence Modus).
• Deep MBIST expertise with repair, SCAN, IJTAG (IEEE 1687) and boundary scan (IEEE 1149.1/6).
• Experience with FinFET nodes (7nm/5nm or below) and multi-voltage designs.

Responsibilities

• Architect end-to-end DFT for complex SoCs, including Hierarchical DFT and boundary scan.
• Develop IST and POST strategies to ensure chip health in remote edge data centers.
• Oversee scan insertion, ATPG (Stuck-at/Transition/Path Delay) and Memory/Logic BIST.
• Collaborate with Design, Physical Design, and Yield to maximize test coverage while minimizing overhead and power.
• Lead bring-up and debug on ATE to root-cause failures and optimize test time.

Skills

DFT leadership

Boundary Scan

MBIST

ATPG

Timing analysis

Edge data center reliability

Power-aware DFT

Education

Bachelor’s degree in a related field

Tools

Synopsys TestMAX

Siemens/Mentor Tessent

Cadence Modus

Job description

EnCharge AI is seeking a Lead DFT Engineer to architect test strategies for edge-to-cloud chips, balancing high-performance processing with power efficiency in remote environments.

You will lead DFT architecture, IST/POST methods, and oversee ATPG and MBIST efforts, collaborating with Design, Physical Design, and Yield teams to achieve high test coverage with minimal area and power impact.