Senior ASIC RTL Design Engineer, AI Hardware

Fdetimes; Sunnyvale (CA); Hybrid; USD 200,000 - 290,000; Full time

Job summary

Cerebras Systems is seeking a Senior Front-End Design Engineer to lead RTL design for the Wafer Scale Engine. You will work with design verification, physical design, software and system teams to deliver high-performance, power-efficient chip implementations from concept to production.

The role requires a Master’s degree in CS/EE and 8+ years of experience in RTL designs, with strong experience in front-end chip integration, networking, and collaboration with external vendors.

Qualifications

• Master's degree in Computer Science, Electrical Engineering, or equivalent.
• 8+ years of experience delivering complex, high-performance RTL designs.
• Experience with Front End Chip integration and third-party IP integration.
• Experience with networking stacks including TCP/IP, RDMA and Ethernet.
• Knowledge of PCIe, CPU interfaces and Serdes technology.
• Working knowledge of scripting tools: Python, TCL.

Responsibilities

• Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.
• Collaborate with PD, Design verification, DFT, software and system teams to achieve performance and power goals.
• Debug silicon-level functional, timing, and power issues during bring up.
• Work with external vendors to manage ASIC development.

Skills

RTL design

Front End Chip integration

External vendors

Networking (TCP/IP, RDMA, Ethernet)

PCIe, CPU interfaces, Serdes

Python

TCL

Education

Master's degree in CS/EE

Tools

FPGA toolchain

Job description

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services.

This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.

Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.

About The Role

As a senior front-end design engineer, you will be a key part of the world-class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE). This role requires deep expertise in RTL design and integration, with a strong focus on delivering high-performance, power-efficient, and scalable solutions. You will collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of building WSE systems.

Responsibilities

• Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.
• Work closely with PD team members for design closure to meet PPA goals.
• Work closely with Design verification and DFT teams for achieving the best functional and test coverage.
• Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.
• Debug silicon-level functional, timing, and power issues during bring up.
• Requirements
• Master's degree in Computer Science, Electrical Engineering, or equivalent.
• Can work in a hybrid work environment.
• 8+ years of experience in delivering complex, high performance high quality RTL designs.
• Experience with Front End Chip integration and third-party IP integration.
• Demonstrated experience in high-performance computing, GPU/CPU designs, machine learning or related fields.
• Proven track record of multiple silicon success.
• Experience collaborating with external vendors.
• Networking stack experience including TCP/IP, RDMA and Ethernet.
• Knowledge of PCIe, CPU interfaces and Serdes technology.
• Working knowledge of scripting tools : Python, TCL.

Assets

• Experience with FPGA development toolchain, including Place and Route, Floor planning and Timing Analysis is a plus.
• Experience managing external ASIC vendor through product development cycle.

Location: Sunnyvale, CA (Open to Remote)

The base salary range for this position is $200,000 to $290,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

Why Join Cerebras

People who are serious about software make their own hardware. At Cerebras, we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we've reached an inflection point in our business. Members of our team tell us there are five main reasons they joined Cerebras:

• Build a breakthrough AI platform beyond the constraints of the GPU.
• Publish and open source their cutting-edge AI research.
• Work on one of the fastest AI supercomputers in the world.
• Enjoy job stability with startup vitality.
• Our simple, non-corporate work culture that respects individual beliefs.

Find out more about what it's like to work at Cerebras here!

Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them.

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