Senior ASIC Emulation Engineer

K2 Space; Seattle (WA); On-site; USD 170,000 - 250,000; Full time

Benefits offered by this job

Equity

Medical/dental/vision insurance

Paid time off

Parental leave

Job summary

K2 Space is seeking a Senior ASIC Emulation Engineer to lead bring-up and optimization of pre-silicon emulation platforms. You will collaborate with architecture, RTL, DV, firmware, and physical design teams to enable high‑fidelity hardware/software co-development and accelerate verification cycles.

This is a hands‑on role with ownership over emulation strategy and workflows. You will work with Palladium/ZeBu/Veloce platforms, build robust emulation capabilities, and support system-level testing

Qualifications

• B.S./M.S. in Electrical Engineering or related field.
• 5+ years of experience in ASIC/SoC development, focused on emulation.
• Strong knowledge of SystemVerilog, digital logic, RTL flows, DV methodologies, and lifecycle.
• Hands-on expertise with emulation platforms (Palladium, ZeBu, Veloce).
• Proficiency with scripting languages (Python, Perl, TCL) for automation and tooling.
• Experience with hardware/software interfaces, embedded processors, firmware bring-up, and C/C++-based system-level testing.
• Familiarity with APB/AHB/AXI, JTAG, SPI buses.
• Experience driving cross-functional debug involving RTL, DV, firmware, physical design, and validation.
• Understanding of pre- and post-silicon debug methodologies.

Responsibilities

• Build, integrate, and maintain full-chip, multi-chip and system-level emulation models.
• Define and evolve emulation strategy, methodology, and workflows.
• Work with RTL engineers to compile, map, and optimize designs for emulation performance.
• Develop and integrate transactors, BFMs, speed adapters, and virtualization interfaces.
• Support system-level testing in emulation with HW/SW integration.
• Accelerate verification throughput by running high-value tests in emulation.
• Enable firmware, bootloader, driver, and software teams by providing emulation platforms.
• Run emulation workloads, triage failures, and perform root-cause analysis.
• Maintain automation for compile flows, regression management, and CI.
• Participate in architecture reviews, microarchitecture discussions, and emulation best practices.
• Support silicon bring-up and post-silicon validation through test reuse and diagnostics.

Skills

SystemVerilog

RTL design

DV methodologies

Python scripting

C/C++ testing

Bus protocols (PCIe/Ethernet)

Cross-functional collaboration

Education

B.S./M.S. in Electrical Engineering

Tools

Palladium

ZeBu

Veloce

Job description

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.

The Role

We are seeking a Senior ASIC Emulation Engineer who will lead the bring-up, deployment, and optimization of our pre-silicon emulation platforms. You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and silicon validation teams to enable high‑fidelity hardware/software co-development and accelerate verification cycles. This is a hands‑on role with high ownership, deep technical engagement, and the opportunity to shape first‑generation silicon and system methodology.

Responsibilities

• Build, integrate, and maintain full-chip, multi-chips and system-levelemulationmodels on platforms such as Palladium, ZeBu, or Veloce.
• Define and evolveemulationstrategy, methodology, and workflows across the ASIC organization.
• Work with RTL engineers to compile, map, and optimize designs foretulationperformance, capacity, and stability.
• Develop and integrate transactors, BFMs, speed adapters, and virtualization interfaces to support diverse system use cases.
• Support system‑level testing inemulationby enabling full hardware/software integration, validating complex use cases, and ensuring the environment can run representative end‑to‑end workloads.
• Accelerate overall verification throughput by helping DV team run targeted and high‑value tests inemulation, including adapting DV content and optimizing flows to reduce simulation bottlenecks.
• Enable firmware, bootloader, driver, and software teams by providing robustemulationplatforms and assisting in HW/SW integration debug.
• Runemulationworkloads, triage failures, perform root‑cause analysis, and collaborate across design and verification to resolve issues.
• Maintain and enhance automation for compile flows, regression management, and continuous integration.
• Participate in architecture reviews, microarchitecture discussions, and influence design-for-emulationbest practices.
• Support silicon bring‑up and post‑silicon validation through test reuse, diagnostics, and pre/post‑silicon correlation.
• Manage interactions with external IP providers oremulationpartners when needed.

Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in ASIC/SoC development, focused on emulation
• Solid understanding of SystemVerilog, digital logic, RTL flows, DV methodologies, and ASIC development lifecycles.
• Hands‑on expertise with majoremulationplatforms (Palladium, ZeBu, Veloce), including model build, debug and performance optimization
• Proficiency with scripting languages (Python, Perl, TCL) for automation and tooling.
• Experience with hardware/software interfaces, embedded processors, firmware bring‑up, and C/C++‑based system‑level testing.
• Familiarity with industry‑standard buses and protocols such as APB/AHB/AXI, JTAG, SPI.
• Experience driving cross‑functional debug involving RTL, DV, firmware, physical design, and validation teams.
• Understanding of pre‑and post‑silicon debug methodologies and correlation workflows.

Nice to Have

• Experience with FPGA prototyping platforms (HAPS, Protium, custom FPGA boards).
• Experience with low‑power modes and power‑awareemulation.
• Experience with analog/mixed‑signal behavioral models inemulationenvironments.
• Experience with SERDES and high‑speed data protocols such as PCIe, Ethernet, USB, or multi‑gigabit PHYs.

Compensation and Benefits:

• Base salary range for this role is $170,000 – $250,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non‑traditional career twists and turns are encouraged!

If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.

Export Compliance

As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.”

To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about ITAR here.

K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.