Senior ASIC Design Verification Engineer - Terawave

Blue Origin; Texas; Vor Ort; USD 230.000 - 323.000; Vollzeit

Benefits dieser Stelle

Medical benefits

Dental benefits

Vision benefits

Parental leave

Disability insurance

401(k) match

Education support

Stock options

Paid time off

Zusammenfassung

Blue Origin in Texas is seeking an experienced ASIC/SoC verification engineer to lead verification planning, develop UVM environments, and drive coverage closure. You will translate architecture into verification strategies and mentor junior engineers.

Collaborate with design, firmware, and systems teams, review testbench quality, support bring-up and post‑silicon debugging, and contribute to a high‑assurance space hardware pipeline.

Qualifikationen

• BS or MS in Electrical/Computer Engineering, Computer Engineering, or related field.
• 8+ years ASIC/SoC verification experience.
• Deep hands-on SystemVerilog and UVM expertise.
• Strong verification planning, assertions, and coverage closure.
• Experience verifying complex digital control and datapath logic.
• Proven debugging capability across RTL, testbench, and system interactions.
• Ability to work effectively across multidisciplinary engineering teams.

Aufgaben

• Lead verification planning and execution for complex blocks or subsystems.
• Develop sophisticated UVM environments, reference models, scoreboards, protocol monitors, and assertions.
• Translate architecture and design specifications into comprehensive verification strategies and measurable coverage goals.
• Drive functional coverage closure, regression health, and verification signoff readiness.
• Identify verification gaps, corner cases, and high‑risk scenarios early in the development cycle.
• Collaborate closely with design, systems, DFT, firmware, and physical design teams.
• Review testbench architecture, stimulus quality, and debug methodologies for technical excellence.
• Mentor junior engineers in verification standard processes.
• Support bring‑up, emulation, prototyping, and post‑silicon debug activities as needed.

Kenntnisse

SystemVerilog

UVM

ASIC/SoC verification

Verification planning

Debug RTL/testbench

Ausbildung

B.S./M.S. in Electrical/Computer Engineering

Tools

Formal verification tools

Jobbeschreibung

Application close date: Applications will be accepted on an ongoing basis until the requisition is closed.

Responsibilities

• Lead verification planning and execution for complex blocks or subsystems.
• Develop sophisticated UVM environments, reference models, scoreboards, protocol monitors, and assertions.
• Translate architecture and design specifications into comprehensive verification strategies and measurable coverage goals.
• Drive functional coverage closure, regression health, and verification signoff readiness.
• Identify verification gaps, corner cases, and high‑risk scenarios early in the development cycle.
• Collaborate closely with design, systems, DFT, firmware, and physical design teams.
• Review testbench architecture, stimulus quality, and debug methodologies for technical excellence.
• Mentor junior engineers in verification standard processes.
• Support bring‑up, emulation, prototyping, and post‑silicon debug activities as needed.

Minimum Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, or a related field.
• 8+ years of ASIC/SoC verification experience.
• Deep hands‑on expertise in System Verilog and UVM.
• Strong understanding of verification planning, assertions, and coverage closure.
• Experience verifying complex digital control and datapath logic.
• Proven debugging capability across RTL, testbench, and system interactions.
• Ability to work effectively across multidisciplinary engineering teams.

Preferred Qualifications

• Background in space‑based communications, wireless communications, or modem/baseband hardware.
• Experience verifying LDPC/BCH/FEC blocks, framing engines, beamforming logic, or DSP pipelines.
• Familiarity with formal verification tools and methodologies.
• Experience with low‑power verification, CDC/RDC verification, or reset‑domain behavior.
• Knowledge of high‑speed interface verification and hardware/software interactions.

Base Pay Range

• California applicants: $230,398.00 – $322,556.85.
• Washington applicants: $230,398.00 – $322,556.85.
• Other site ranges may differ.

Benefits

• Medical, dental, vision, basic and supplemental life insurance.
• Paid parental leave.
• Short‑ and long‑term disability.
• 401(k) with up to 5% company match.
• Education Support Program.
• Stock Options for regular employees.
• Paid Time Off: up to four weeks per year; up to 14 company‑paid holidays.

Equal Employment Opportunity

Blue Origin is proud to be an Equal Opportunity/Affirmative Action Employer and is committed to attracting, retaining, and developing a highly qualified and dedicated workforce. Blue Origin hires and promotes people on the basis of their qualifications, performance, and abilities, fostering trust, equality, and teamwork. We provide all qualified applicants and employees with equal opportunities for hire, promotion, and other terms and conditions of employment, regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, age, physical or mental disability, genetic factors, military/veteran status, or any other status or characteristic protected by federal, state, and/or local law. Blue Origin will consider qualified applicants with criminal histories in a manner consistent with applicable federal, state, and local laws, including the Washington Fair Chance Act, the California Fair Chance Act, and the Los Angeles Fair Chance in Hiring Ordinance.