Senior Architect, HPC & DL Networking

Segment (Twilio); Santa Clara (CA); On-site; USD 320,000 - 488,750; Full time

Job summary

NVIDIA seeks a Distinguished Software Architect to co‑design next‑gen data center platforms, focusing on HPC and DL communication libraries. You will research new technologies, design features, and ensure integration with CUDA, NCCL, and UCX within multi‑GPU, multi‑node systems.

The role requires deep HPC experience, leadership across HW/SW teams, and the ability to influence standards and open source efforts. Strong communication across time zones is essential.

Qualifications

• PhD or equivalent experience; more than 15 years of relevant experience in academia or industry.
• Expertise in HPC, parallel programming models (MPI, SHMEM), and at least one communication runtime (MPI, NCCL, NVSHMEM, OpenSHMEM, UCX, UCC).
• Deep understanding of high‑performance networking: Infiniband, Ethernet; network design, topologies, debugging, and performance analysis.
• Strong knowledge in DL fundamentals and their relation to communications, parallel algorithms, fault tolerance, and performance optimization for large clusters.

Responsibilities

• Research new communication technologies and design new features for our communication libraries.
• Propose innovative HW/SW solutions and co‑design with GPU, Networking, and SW architects for seamless integration.
• Inspire changes based on data from proof‑of‑concepts or detailed analysis.
• Drive adoption of new communication technologies across application verticals.
• Collaborate with DL researchers and customers across diverse teams.

Skills

HPC

MPI

SHMEM

CUDA

GPU architecture

DL/ML concepts

C/C++

System design

Education

PhD in Computer Science or Computer Engineering or equivalent

Tools

MPI

NCCL

NVSHMEM

OpenSHMEM

UCX

UCC

Job description

NVIDIA seeks a Distinguished Software Architect to co‑design next‑gen data center platforms, focusing on HPC and DL communication libraries. You will research new technologies, design features, and ensure integration with CUDA, NCCL, and UCX within multi‑GPU, multi‑node systems.

The role requires deep HPC experience, leadership across HW/SW teams, and the ability to influence standards and open source efforts. Strong communication across time zones is essential.