Senior Analog IC Design Engineer | Equity & Stock Options

Apple Inc.; Waltham (MA); On-site; USD 116,000 - 203,000; Full time

Benefits offered by this job

Employee stock purchase plan

Discretionary stock awards

Relocation assistance

Medical and dental coverage

Tuition reimbursement

Job summary

Apple Inc. in Waltham, MA, seeks an IC Designer to craft analog/mixed-signal blocks for next-generation products. You will specify analog IC portions, model architectures, and study transistor-level feasibility for ADC/DAC. This role drives mask design and top-level simulations to validate integration.

Join a team focused on robust test plans, lab measurements, yield analysis, and testability improvements, with a strong emphasis on ESD compliance and design for reliability.

Qualifications

• Involved in specifications of analog portions of IC.
• Behavioral modeling to validate architectures.
• Transistor-level feasibility studies for ADC/DAC blocks.
• Crafting blocks and documenting design towards formal reviews.
• Drive mask design to implement layout view of designs.
• Top-level simulations to validate integration.
• Defining production/bench-level test-plans.
• Taking lab measurements to validate analog designs.
• Driving yield/lab test results to fix bugs.
• Design for ESD compliance.

Responsibilities

• Drive mask design to implement layout view of designs.
• Top-level simulations to validate integration.
• Defining production/bench-level test-plans.
• Take lab measurements to validate analog designs.
• Drive yield/lab test results to drive bug fixes.
• Design for ESD compliance.

Skills

ADC/DAC architectures

Low-noise design

Precision techniques

Device physics knowledge

Analog IC design fundamentals

Education

Bachelor's degree

Tools

C

Matlab

Verilog modeling

Spectrum analyzers

Oscilloscopes

Signal generators

Test equipment

Job description

Apple Inc. in Waltham, MA, seeks an IC Designer to craft analog/mixed-signal blocks for next-generation products. You will specify analog IC portions, model architectures, and study transistor-level feasibility for ADC/DAC. This role drives mask design and top-level simulations to validate integration.

Join a team focused on robust test plans, lab measurements, yield analysis, and testability improvements, with a strong emphasis on ESD compliance and design for reliability.