Semiconductor Layout Designer with Automation

1000 Micron Technology, Inc.; San Jose (CA); On-site; USD 63,369 - 146,025; Full time

Benefits offered by this job

Choice of medical, dental and vision plans

Income protection benefits

Robust paid time-off and holidays

Job summary

1000 Micron Technology, Inc. is seeking a Layout Designer in San Jose, California. In this role, you will be responsible for developing multi-dimensional layouts for semiconductor devices, verifying data integrity, and collaborating with global teams. You will manage logistics and resource allocations while improving layout efficiency through innovative methodologies.

The ideal candidate has an AS degree in Electronics or Electrical Engineering and at least 5 years of experience in semiconductor layout design. Proficiency in EDA tools like Cadence Virtuoso, Synopsys, and Calibre is essential. Strong communication and debugging skills are also required.

Qualifications

• 5+ years of direct experience in semiconductor layout design.
• Deep understanding of EDA tools.
• Ability to debug and collaborate with engineering staff.
• Skilled in layout and planning methodologies.
• Strong verbal and written communication skills.

Responsibilities

• Coordinate logistics and resource allocations to meet deadlines.
• Contribute to management and technical innovation.
• Manage time effectively to ensure quality results.
• Contribute to globally distributed design/layout projects.
• Improve layout efficiency through automation and methodologies.

Skills

Semiconductor layout design

EDA tools (Cadence Virtuoso, Synopsys, Calibre)

Problem debugging and root-cause analysis

Communication skills

Design rules and quality layouts

Physical verification analysis

Education

AS in Electronics, Electrical Engineering or related field

Tools

Cadence Virtuoso

Synopsys

Calibre

Job description

1000 Micron Technology, Inc. is seeking a Layout Designer in San Jose, California. In this role, you will be responsible for developing multi-dimensional layouts for semiconductor devices, verifying data integrity, and collaborating with global teams. You will manage logistics and resource allocations while improving layout efficiency through innovative methodologies.

The ideal candidate has an AS degree in Electronics or Electrical Engineering and at least 5 years of experience in semiconductor layout design. Proficiency in EDA tools like Cadence Virtuoso, Synopsys, and Calibre is essential. Strong communication and debugging skills are also required.