Scientist, Electrical Engineer

L3Harris Technologies; Yorba Linda (CA); On-site; USD 153,000 - 284,000; Full time

Benefits offered by this job

Health and disability insurance

401(k) match

Flexible spending accounts

Employee assistance program

Education assistance

Parental leave

Paid time off

Company-paid holidays

Job summary

L3Harris Technologies in Yorba Linda, CA seeks a Scientist, Electrical Engineer to drive FPGA/ASIC architectures from customer requirements to final solution. The role integrates GPS signal processing, RF design, and system engineering with cross-functional teams across software, hardware, and test disciplines.

Responsibilities include requirements flow-down, architecture definition, and developing qualification plans to ensure customer satisfaction while adhering to program budgets and

Qualifications

• Bachelor's degree with 10+ years of relevant experience, or graduate degree with 7+ years of relevant experience.
• 5+ years' experience in multi-processor system FPGA/ASIC development from RTL to timing closure.
• 5+ years' experience in schematics design capture and PCBA layout using modern EE CAD such as Altium or Mentor Graphics.
• 5+ years' experience with project management and product design team leadership with minimal oversight.
• 6+ years' strong experience with receiver, antenna, or radio design (RF).
• 4+ years' experience with embedded hardware design.
• 2+ years' experience with FPGA design with emphasis in DSP.
• 4+ years' experience with verbal and written skills.
• 7+ Years experience with design tools such as MATLAB/Simulink, P-Spice, Agilent ADS (or AWR), Altium, HFSS; 2+ years with Xilinx tools; Active Secret clearance.

Responsibilities

• Translate customer requirements into architectures and derive downstream requirements for software, FPGA/ASIC, and test teams.
• Develop qualification test plans to verify architecture and solution against customer needs.
• Coordinate with GPS/ RF, software, and hardware teams to meet program budgets and schedules.
• Lead design reviews and contribute to the engineering baseline and program status updates.
• Interface with leadership and multiple engineering teams for technical reviews and progress reporting.
• Participate in product development from concept through integration and test.
• Travel up to 10% as required.

Skills

FPGA/ASIC development

UVM/SystemVerilog

RF design

GPS signal processing

Requirements engineering

Cross-functional leadership

Project management

Verbal communication

Written communication

Systems integration

Education

Bachelor’s Degree in Electrical Engineering or related field

Graduate Degree (MS/PhD) in a relevant field

Tools

MATLAB/Simulink

P-Spice

Agilent ADS

Altium

Mentor Graphics

Ansys HFSS

Xilinx ISE

Xilinx EDK

ModelSim

Job description

L3Harris is dedicated to recruiting and developing high-performing talent who are passionate about what they do. Our employees are unified in a shared dedication to our customers’ mission and quest for professional growth. L3Harris provides an inclusive, engaging environment designed to empower employees and promote work-life success. Fundamental to our culture is an unwavering focus on values, dedication to our communities, and commitment to excellence in everything we do.

L3Harris is the Trusted Disruptor in defense tech. With customers’ mission-critical needs always in mind, our employees deliver end-to-end technology solutions connecting the space, air, land, sea and cyber domains in the interest of national security.

Job Title: Scientist, Electrical Engineer

Job Code: 45402

Job Location: Yorba Linda, CA.

Work Schedule: 4/10 Employees work 10 hour days, 4 days a week

Job Description

As a Scientist Electrical Engineer, the candidate must have experience with FPGA and ASIC Design, able to work from customer requirements to derive additional requirements, define the architecture of a possible solution based on requirements, setup a requirements schema & link requirements to documents (systems/subsystem specification, hardware/FPGA, ASIC architecture description document, etc.) and flow down applicable requirements to other groups (software, ASIC, & test) so that they can contribute to realize the end solution based on the proposed architecture. The Scientist, Electrical Engineer will also oversee the development a qualification test plan that will ensure that the architecture and solution satisfy the customers’ requirements. The Scientist EE will also work with subject matter experts in the areas of GPS signal processing, anti-jam signal processing, other hardware design team members, control software, and government qualification standards. As a Scientist EE, the candidate is expected to understand each aspect of the technology used in the proposed solution. The Lead EE also must work with the cost account manager, program management, and project management to develop the solution within the program’s budget and schedule.

Essential Functions

• Requires comprehensive level knowledge of FPGA, ASIC and Digital circuit design, including direct experience with UVM/System Verilog driven simulation and Palladium-based emulation.
• Experience with RF systems, ideally GPS receivers
• Able to contribute to providing innovative Electrical Engineering solutions consistent with business development plans.
• Ability to develop circuit designs, requirements, design descriptions, verification plans/procedures, customer CDRLs to meet program schedules.
• Ability to support cross functional teams for cross functional conflict resolution, Root Cause Analysis, blank page architecture developments and design
• Ability to contribute to algorithm development, analysis, implementation, system architecture, verification, and Test with emphasis on military GPS electronics.
• Ability to contribute to execution of design, build, integration and test activities, problem resolution and verifying that the deliverable products meet all program and customer requirements.
• Ability to provide project management reports as required, support senior level and customer reviews as necessary.
• Ability to provide inputs and reviews of the engineering technical baseline as part of proposal efforts.
• Ability to interface with the program’s leadership and other teams (SW, Systems, ME, and Test) on a frequent basis, conduct or participate in customer and/or program technical review presentations, and provide progress status updates on work products.
• Ability to participate or lead in the product development process including design reviews.
• 5 to 10% Travel required.

Qualifications

• Bachelor’s Degree and a minimum of 10 years of prior relevant experience, or Graduate Degree and a minimum of 7 years of prior related experience. In lieu of a degree, a minimum of 13 years of prior related experience.
• 5+ years’ experience in multi-processor system FPGA/ASIC development from RTL design through structural netlist timing closure including CDC and UPF.
• 5+ years’ experience in schematics design capture and PCBA Layout using modern EE CAD such as Altium or Mentor Graphics.
• 5+ years’ experience with project management and product design team leadership guided by individual annual goals and objectives with minimal oversight or direction; working in a team environment as an individual contributor.
• 6+ years’ strong experience with receiver, Antenna, or Radio design (i.e. RF).
• 4+ years’ experience with embedded Hardware design.
• 2+ years’ experience with FPGA design with emphasis in digital signal processing (DSP).
• 4+ years’ experience demonstrating strong verbal and written skills.
• 7+ Years experience with design tools such as MATLAB/Simulink, P-Spice, Agilent ADS (or AWR), Schematics Capturing/PCBA Layout tools such as Altium, and Ansys HFSS. 2+ Years’ experience with FPGA design tools such as Xilinx ISE, Xilinx EDK, and ModelSim. Active Secret Security Clearance.

Preferred Additional Skills

• Strong familiarity with GPS Module design and topology.
• Advanced with High-speed Analog design methodologies.
• Advanced in MS Office, design tools such as Simulink/MATLAB, P-Spice, Altium (Schematics Capturing & PCBA Layout), Agilent ADS (or AWR), and Ansys HFSS.
• Familiar with FPGA design methodologies.
• Proficient with DO-254 design.
• Strong Background with Linux-based Tool Chain Management and Performance Monitoring

In compliance with pay transparency requirements, the salary range for this role in California is Min $153,000.00 - $284,000.00 Max. This is not a guarantee of compensation or salary, as final offer amount may vary based on factors including but not limited to experience and geographic location.

Benefits

• health and disability insurance
• 401(k) match
• flexible spending accounts
• EAP
• education assistance
• parental leave
• paid time off
• company-paid holidays

The specific programs and options available to an employee may vary depending on date of hire, schedule type, and the applicability of collective bargaining agreements.

L3Harris Technologies is proud to be an Equal Opportunity Employer. L3Harris is committed to treating all employees and applicants for employment with respect and dignity and maintaining a workplace that is free from unlawful discrimination. All applicants will be considered for employment without regard to race, color, religion, age, national origin, ancestry, ethnicity, gender (including pregnancy, childbirth, breastfeeding or other related medical conditions), gender identity, gender expression, sexual orientation, marital status, veteran status, disability, genetic information, citizenship status, characteristic or membership in any other group protected by federal, state or local laws. L3Harris maintains a drug-free workplace and performs pre-employment substance abuse testing and background checks, where permitted by law.

Please be aware many of our positions require the ability to obtain a security clearance. Security clearances may only be granted to U.S. citizens. In addition, applicants who accept a conditional offer of employment may be subject to government security investigation(s) and must meet eligibility requirements for access to classified information.