Remote Formal Verification Engineer: RTL & Theorem Proving

MatX; Mountain View (WY); Hybrid; USD 150,000 - 425,000; Full time

Benefits offered by this job

Equity in compensation

Health & Wellness

Paid time off

Parental leave

Learning & development

401K

Remote work flexibility

Job summary

MatX is building the worlds most efficient AI stack, from hardware to compiler IR. We are seeking a Formal Verification Engineer to bring rigorous guarantees across RTL, memory subsystems, and interconnects.

You’ll apply model checking with JasperGold or VC-Formal, develop machine‑checked proofs for transformations, and embed HDL/IR into theorem provers (Lean 4, Coq, Isabelle/HOL) to establish functional correctness.

Qualifications

• Hands-on hardware model checking (SVA/PSL) and proving at block/subsystem level.
• Experience with at least one interactive theorem prover (Lean, Coq, Isabelle/HOL, Agda, or similar).
• Experience embedding an HDL/IR into a theorem prover (HDL, compiler IR, ISA, or similar).
• Experience with compiler correctness proofs or verified compilation is a strong plus.

Responsibilities

• Apply model checking to RTL blocks, memory subsystems, and interconnects.
• Develop machine-checked proofs for compiler transformations and lowering passes.
• Embed HDL/IR into theorem provers to prove functional correctness and microarchitectural properties.
• Collaborate with architecture, compiler, and silicon verification teams to translate properties into proof obligations.
• Drive methodology to integrate formal tools into existing practices.

Skills

Model checking

Proof tooling

Interactive theorem proving

Lean 4

Coq/Isabelle/HOL

HDL/IR embeddings

Compiler correctness

RTL understanding

Tools

JasperGold

VC-Formal

SymbiYosys

Job description

MatX is building the worlds most efficient AI stack, from hardware to compiler IR. We are seeking a Formal Verification Engineer to bring rigorous guarantees across RTL, memory subsystems, and interconnects.

You’ll apply model checking with JasperGold or VC-Formal, develop machine‑checked proofs for transformations, and embed HDL/IR into theorem provers (Lean 4, Coq, Isabelle/HOL) to establish functional correctness.