Reliability Infrastructure Technician, Raxium

Google; Fremont (CA); On-site; USD 100,000 - 140,000; Full time

Benefits offered by this job

Equity

Bonus target 15%

Benefits

Job summary

Google's Raxium reliability lab seeks a Reliability Engineering Technician to operate stress chambers, run reliability tests, and perform initial troubleshooting. You will work closely with engineering teams to support reliability stress operations, ensure equipment uptime, and assist product testing in a state-of-the-art semiconductor fab in Silicon Valley.

Individuals will perform precision soldering and mechanical assembly, manage MES/WIP tasks, and contribute to SOPs and maintenance

Qualifications

• Associate's degree in Electrical Engineering, Electronics, Mechanical Engineering, or equivalent practical experience.
• 2 years of experience working in a semiconductor lab or manufacturing environment.
• 1 year of experience troubleshooting electromechanical systems for reliability stress station, chambers, or automated test equipment.
• Experience performing precision soldering and mechanical assembly.

Responsibilities

• Learn more about benefits at Google .
• Support reliability stress testing within the lab, manage MES transactions, and synchronize WIP tracking, bridging operator and technician responsibilities.
• Drive initial debug activities of product failures with FA, test, and reliability engineers to submit and track FA job requests.
• Own new stress code validation, perform first-pass reliability data analysis, create automation and reporting for data analysis, chamber profiles, and parameter tracking.
• Lead the setup of new stress chambers and stations installations, supporting electrical rack installation, software configuration, and precision mechanical/optical assembly
• Drive process consistency by creating detailed work instructions (SOPs), conducting equipment audits/qualifications, maintaining stress chamber documentation.

Skills

Reliability testing

WIP tracking

MES transactions

SOP writing

Lab troubleshooting

Electrical/electronics

Python basics

Linux/Unix

Google Workspace

Manual dexterity

Education

Associate's degree in engineering

Bachelor's degree in EE

Tools

MES software

Laboratory automation

Data analytics tools

Job description

Minimum qualifications

• Associate's degree in Electrical Engineering, Electronics, Mechanical Engineering, or equivalent practical experience.
• 2 years of experience working in a semiconductor lab or manufacturing environment.
• 1 year of experience troubleshooting electromechanical systems for reliability stress station, chambers, or automated test equipment.
• Experience performing precision soldering and mechanical assembly.

Preferred qualifications

• Bachelor's degree in Electrical Engineering, Electronics, Mechanical Engineering, or equivalent degree.
• 3 years of experience working in a semiconductor lab or manufacturing environment.
• Experience in operating and troubleshooting reliability stress chambers.
• Demonstrated experience writing technical documentation or maintenance checklists.
• Familiarity with Linux/Unix command line environments, proficiency in Google Workspace (Docs, Sheets, Slides), with a basic familiarity with Python.
• Manual dexterity and attention to detail for handling sensitive semiconductor components.

About The Job

As a Reliability Engineering Technician, you will be responsible for running the operation in Raxium Reliability Lab as a skilled operator and also a technical troubleshooter. You will operate our Reliability stress chambers; execute reliability stress tests, and perform initial troubleshooting for any failure. You will work closely with engineering teams to support reliability stress operations, ensure equipment uptime, and collaborate with test teams for product testing.

Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $99000 - $140000 (USD) + 15% bonus target + equity + benefits

Responsibilities

Learn more about benefits at Google .

• Support reliability stress testing within the lab, manage Manufacturing Execution System (MES) transactions, and synchronize Work-in-Progress (WIP) tracking, effectively bridging operator and technician responsibilities.
• Drive initial debug activities of product failures in the reliability lab, coordinate with FA, test, and reliability engineers to submit and track formal FA job requests.
• Own new stress code validation, execute first pass reliability data analysis, create automation and reporting for data analysis, chamber profiles, lab environmental parameter tracking.
• Lead the setup of new stress chambers and stations installations, supporting electrical rack installation, software configuration, and precision mechanical/optical assembly
• Drive process consistency by creating detailed work instructions (SOPs), conducting equipment audits/qualifications, maintaining stress chamber documentations.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .