Process Engineer, Gold-To-Gold Interconnect & Flip Chip Assembly (Starlink/Akoustis)

SpaceX; Texas; Presencial; USD 90.000 - 130.000; Jornada completa

Descripción de la vacante

SpaceX is seeking a hands-on Process Engineer to develop and optimize advanced IC assembly processes, with emphasis on Gold-to-Gold interconnect and thermosonic flip-chip bonding. You’ll move processes from prototype to production, collaborating with equipment, package engineering, and reliability teams.

You will define DOE windows, drive NPI, and ensure bond integrity, contact resistance, and mechanical strength while supporting related assembly steps and materials selection.

Formación

• Bachelor's degree in chemical engineering, materials science, mechanical engineering, or related field.
• 2+ years hands-on semiconductor assembly or IC packaging experience.
• 3+ years hands-on IC assembly/advanced packaging experience.

Responsabilidades

• Develop and qualify GGI and thermosonic flip-chip/die-attach processes with DOE to control bond integrity, contact resistance, and mechanical strength.
• Develop gold stud bump, gold bump, and gold-to-gold interconnect processes and evaluate bond quality.
• Optimize vacuum mold lamination and encapsulation; troubleshoot voiding, warpage, delamination, and incomplete fill.
• Support wafer/die handling, cleaning, underfill, reflow, and inspection steps.
• Select and characterize assembly materials for bond strength, adhesion, thermal performance, and reliability.
• Specify and qualify assembly equipment with suppliers.
• Run DOEs, capability studies, and SPC; write process specs, work instructions, control plans, FMEAs, and qualification reports.
• Drive NPI from prototype to production release; assist failure analysis (X-ray, SAM, optical, cross-section, SEM).
• Correlate process settings to electrical, mechanical, and reliability results; apply DFM and manage schedules, risks, and production readiness.

Conocimientos

GGI interconnect

Thermosonic bonding

Gold stud bumping

DOE / SPC

Root-cause analysis

Six Sigma

Interconnect metrology

AutoCAD

ANSYS

COMSOL

MATLAB

Python

Educación

Bachelor's degree in chemical engineering

Herramientas

AutoCAD

ANSYS

COMSOL

MATLAB

Python

JMP

Minitab

Descripción del empleo

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

Akoustis is now operating as a wholly owned subsidiary of SpaceX providing industry leading RF filters using patented XBAW technology to help drive the mission of making human life multi-planetary, while also connecting the world through Starlink. Our work helps further the impact that Starlink is already making on millions of users around the world, while allowing us to broaden that reach dramatically and continue connecting the unconnected here on earth.

We are looking for a hands-on Process Engineer to develop, optimize, qualify, and implement advanced IC assembly processes, with a focus on Gold-to-Gold Interconnect (GGI) and thermosonic flip-chip bonding. You will take processes from early prototype through production ramp, working directly with equipment and with package engineering, design, manufacturing, reliability, materials, and supply-chain partners.

RESPONSIBILITIES

• Develop and qualify GGI and thermosonic flip-chip / die-attach processes, including bond force, temperature, ultrasonic energy, bond time, alignment, parallelism, and tool selection; establish process windows with DOE to control bond integrity, contact resistance, and mechanical strength
• Develop gold stud bump, gold bump, and gold-to-gold interconnect processes and evaluate bond quality and process capability
• Develop and optimize vacuum mold lamination and related encapsulation (material selection, vacuum, temperature, pressure, time, and cure); troubleshoot voiding, delamination, die shift, warpage, incomplete fill, and bleed
• Support related assembly steps as needed: wafer/die handling, placement, plasma/surface cleaning, underfill, reflow, singulation, laser marking, and inspection
• Select and characterize assembly materials (adhesives, mold compounds, substrates, interconnect materials) for impact on bond strength, adhesion, thermal performance, warpage, and reliability
• Specify, evaluate, install, and qualify assembly equipment (flip-chip bonders, thermosonic bonders, vacuum laminators, plasma, and inspection tools) with suppliers
• Run DOEs, capability studies, and SPC on critical parameters; write process specs, work instructions, control plans, FMEAs, and qualification reports
• Drive NPI from prototype through qualification and production release; perform root-cause analysis and support failure analysis (X-ray, SAM, optical, cross-section, SEM)
• Correlate process settings to electrical, mechanical, and reliability results; apply DFM and own schedules, risks, and production readiness for assigned technologies

BASIC QUALIFICATIONS

• Bachelor's degree in chemical engineering, materials science, mechanical engineering, or other engineering discipline
• 2+ years of hands-on semiconductor assembly, IC packaging, or electronics manufacturing experience (Internship or extracurricular experience is applicable)

PREFERRED SKILLS AND EXPERIENCE

• 3+ years of hands-on IC assembly or advanced packaging experience, including direct GGI or similar gold-based interconnect work
• Hands-on thermosonic flip-chip bonding (force, temperature, ultrasonic power, time, alignment, tooling) and gold stud bumping, gold bumps, or gold-to-gold interfaces
• Vacuum mold lamination or advanced encapsulation with mold sheets, thermally conductive or epoxy molding compounds, or underfills
• Understanding of plasma/surface preparation, organic/ceramic/leadframe/wafer-level substrates, warpage, CTE mismatch, thermal-mechanical stress, adhesion, and delamination
• DOE, SPC, Cp/Cpk, root-cause analysis, FMEA, Six Sigma, and control plans
• Inspection and metrology (X-ray, SAM, optical microscopy, profilometry, cross-section) and interconnect characterization (contact resistance, shear/pull, bond integrity)
• Package reliability testing and standards (JEDEC, IPC), plus experience supporting OSATs or contract manufacturers through development, qualification, and ramp
• CAD (AutoCAD) and familiarity with simulation tools (ANSYS, COMSOL, or similar) is a plus; data analysis with JMP, Minitab, MATLAB, or Python is a plus
• Experience qualifying new assembly equipment and tooling and troubleshooting issues directly on the manufacturing floor

ADDITIONAL REQUIREMENTS

• Onsite in Bastrop, TX (not remote or hybrid)
• Up to 20% domestic and international travel for supplier and manufacturing support
• Willingness to work extended hours or weekends to support key milestones
• Ability to work in a semiconductor manufacturing environment, follow safety and cleanroom requirements, and perform light physical tasks (including lifting up to 25 lbs and handling wafers, substrates, packages, tooling, and assembly samples)
• Strong written and verbal communication skills with engineering, manufacturing, suppliers, and management

ITAR REQUIREMENTS:

• To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. * 1157, or (iv) Asylee under 8 U.S.C. * 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceX's Affimative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to [e-mail].