Principal Solutions Architect – Semiconductor Test

Nvidia Corporation; Santa Clara (CA); On-site; USD 216,000 - 345,000; Full time

Benefits offered by this job

Equity

Generous benefits package

Competitive salary

Job summary

Nvidia Corporation is seeking a Staff/Principal Solutions Architect to lead the technical strategy for semiconductor test operations in Santa Clara, California. The role involves defining comprehensive test strategies and improving test infrastructure while partnering with multiple teams for complex device portfolios.

The ideal candidate should have over 15 years of experience in semiconductor test engineering, extensive knowledge in areas like ATE architecture, and proficiency in scripting languages. A competitive salary range of USD 216,000 to USD 345,000 is offered, along with equity and benefits.

Qualifications

• 15+ years of hands-on semiconductor test engineering experience.
• Extensive knowledge in ATE platform architecture and test program development.
• Proficiency in test-related scripting and automation.

Responsibilities

• Define the comprehensive test development strategy across wafer-level and package-level testing.
• Lead architectural trade-off decisions on test coverage, cost of test, and quality escapes.
• Mentor senior and principal test engineers.

Skills

Hands-on semiconductor test engineering

ATE platform architecture

DFT methodology

Yield analysis

Test data/ML analytics

Education

MSEE, MSCE, MSCS, or related field

Tools

Python

Perl

C++

Job description

We are seeking a Staff/Principal Solutions Architect to define and lead the technical strategy for semiconductor test. This covers wafer and package test operations from start to finish. This senior individual contributor role is central to our manufacturing and product engineering teams. You will lead the architectural vision for device testing from wafer probe to final package test. Your directive includes modernising test infrastructure, improving yield, and embedding data‑driven intelligence throughout the test lifecycle. You will partner closely with development, process, product engineering, and manufacturing teams across sites to ensure our test strategy scales with increasingly complex device portfolios.

What You'll be doing:

• Define the comprehensive test development strategy across wafer‑level (probe/ATE) and package/final/qual test for new and existing product families.
• Lead architectural trade‑off decisions on test coverage, test time, cost of test, and quality escapes across the full test flow.
• Establish architectural guidelines for the test program, Test Methods/Class structure, modularity, and reuse across ATE platforms (Advantest, Teradyne, etc.).
• Serve as the senior liaison between build and test engineering for DFT architecture decisions - scan, BIST, JTAG, boundary scan, and embedded compression.
• Influence SoC and IP build reviews to ensure testability, observability, and debug‑ability.
• Drive adoption of AI/ML techniques for yield learning, outlier detection, predictive binning, and test time optimization.
• Define and maintain test roadmaps aligned to device technology roadmaps and manufacturing scale targets.
• Mentor senior and principal test engineers; cultivate technical standards and guidelines across the test organisation.
• Engage with ATE vendors, test IP providers, and industry consortia (SEMI, JEDEC, IEEE) on emerging standards and technology directions.

What we need to see:

• 15+ years of hands‑on semiconductor test engineering experience within a fab, IDM, or OSAT environment.
• Extensive knowledge in at least three of the following areas: ATE platform architecture, test program development, DFT methodology, yield analysis, or test data/ML analytics.
• Skilled in leading ATE platforms such as Advantest V93000, Teradyne UltraFLEX/ETS, or similar systems.
• Strong background in DFT architectures - scan compression, MBIST, LBIST, JTAG, and related methodologies.
• Experience with mixed‑signal, RF, or high‑speed I/O test is highly valued.
• Proficiency in test‑related scripting and automation (Python, Perl, C++, or platform‑native languages).
• Proven ability to lead multi‑site technical initiatives involving multi‑functional teams and influence without direct authority.
• MSEE, MSCE, MSCS, or related field (or equivalent experience).

Ways to stand out from the crowd

• Experience applying ML/AI to yield analysis, PAT/GDBN outlier screening, or adaptive test.
• Knowledge of test data formats (STDF, ATDF) and analytics tools (JMP, Spotfire, or custom).
• Exposure to advanced packaging test challenges (2.5D/3D, chiplets, KGD).
• Prior engagement with SEMI standards committees or ATE vendor co‑development programs.
• Ph.D or equivalent experience in related field.

With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most thoughtful and dedicated people in the world working for us. Due to unprecedented growth, our best‑in‑class engineering teams are rapidly growing. If you’re a creative and autonomous engineer with a real passion for technology, we want to hear from you.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 216,000 USD – 345,000 USD.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until June 5, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal‑opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.