Principal SoC DFT Engineer, HBM

Micron Technology, Inc.; Folsom (CA); On-site; USD 199,000 - 347,000; Full time

Job summary

Micron Technology, Inc. seeks an experienced HBM SoC DFT Engineer. You will own DFT architecture, implement test logic, and drive signoff across full-chip designs, collaborating with RTL, physical design, and verification teams to ensure robust test solutions from pre-silicon through tapeout.

You will work with MBIST/LBIST, JTAG boundary scan, and ATPG concepts, while mentoring junior engineers and contributing to future HBM generations with scalable, manufacturable test flows.

Qualifications

• Bachelor’s degree required in EE, CE, or related field.
• 10+ years of SoC DFT/implementation experience.
• Strong hands-on DFT architecture and signoff expertise.

Responsibilities

• Own SoC-level DFT implementation for HBM base-die designs.
• Drive DFT architecture definition early in design cycle.
• Implement DFT logic at block, subsystem, and full-chip levels.
• Own DFT flow execution and signoff (lint, CDC, ATPG).
• Collaborate with physical design to optimize DFT for timing and routing.
• Work with verification, product engineering, test, and manufacturing teams.
• Support pre-silicon debug and post-silicon yield analysis.
• Mentor junior engineers and drive future DFT improvements.
• Develop Gen-AI driven tools and methodologies for DFT workflows.

Skills

SoC DFT architecture

MBIST/LBIST

JTAG/boundary scan

ATPG concepts

RTL-to-GDS flows

Scripting: Python/Tcl/Perl

RTL debugging

Problem solving

Cross-functional collaboration

Memory systems (DRAM/HBM)

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field

Tools

Siemens EDA

Synopsys

Cadence

Job description

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

As an HBM SoC DFT Engineer within the Heterogeneous Integration Group (HIG), you will be responsible for the DFT architecture, implementation, and signoff of complex HBM base-die System-on-Chip (SoC) designs. This role is part of the SoC execution team, working closely with RTL design, verification, physical design, and product engineering to ensure robust, scalable, and manufacturable test solutions from pre-silicon development through tapeout and product bring-up.

Responsibilities Will Include, But Are Not Limited To

• Own SoC-level DFT implementation including scan, MBIST, LBIST (as applicable), boundary scan (JTAG), and test access architectures for HBM base-die designs.
• Drive DFT architecture definition early in the design cycle, ensuring alignment with SoC integration, floorplanning, timing, power, and physical design constraints.
• Implement and integrate DFT logic at the block, subsystem, and full-chip levels, working closely with RTL and integration teams.
• Own DFT flow execution and signoff, including lint, CDC, DFT rule checks, ATPG readiness, and coverage closure.
• Collaborate with physical design teams to ensure DFT solutions are optimized for placement, routing, timing closure, and DRC/LVS signoff.
• Work closely with verification, product engineering, test, probe, and manufacturing teams to ensure testability, diagnosability, and smooth silicon bring-up.
• Support pre-silicon debug of DFT-related issues and assist with post-silicon bring-up and yield/debug analysis.
• Partner with CAD and methodology teams to define, improve, and standardize DFT flows across HBM SoC programs.
• Maintain technical expertise and mentor junior engineers as appropriate.
• Drive innovation into future HBM generations with a focus on quality, scalability, and manufacturability.
• Develop Gen-AI driven tools, workflows, and methodologies that leverage Agentic AI.

Successful Candidates For This Position Will Have

• Strong hands-on experience with SoC DFT architecture and implementation.
• Experience with scan insertion, MBIST/LBIST architectures, JTAG/boundary scan, and ATPG concepts.
• Familiarity with full RTL-to-GDS SoC flows, including interaction between DFT, synthesis, STA, and physical design.
• Experience working with large, complex SoCs involving multiple IPs and subsystems.
• Proficiency with industry-standard EDA tools from Siemens, Synopsys, and/or Cadence for DFT and implementation.
• Strong RTL debugging and design analysis skills.
• Familiarity with scripting languages (Python, Tcl, Perl, etc.) for flow automation.
• Excellent problem-solving and analytical skills.
• Strong written and verbal communication skills and the ability to collaborate across global, cross-functional teams.
• Familiarity with memory systems (DRAM/HBM) and JEDEC specifications is a strong plus.

Required Experience

• Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of relevant experience in SoC design, DFT, or implementation for complex digital ASICs or SoCs.
• Job title and level can scale depending on experience and qualifications.

The US base salary range that Micron Technology estimates it could pay for this full-time position is: $199,000.00 - $347,000.00 a year.

Additional Compensation May Include Benefits, Bonuses And Equity.

Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.