Principal Product Engineer

Celero Communications; Irvine (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications is looking for a Principal Product Engineer to drive productization strategies for advanced coherent DSP integrated circuits in Irvine, California. This role involves hands-on work within engineering and operations teams, ensuring successful product transitions from development to high-volume manufacturing.

The ideal candidate has over 10 years of experience in IC lifecycle roles, with a strong focus on reliability engineering and NPI execution. The position offers a competitive salary range of $150,000 - $250,000 annually, based on qualifications.

Qualifications

• 10+ years of experience in product engineering or related IC lifecycle roles.
• Strong background in reliability qualification and failure analysis.
• Proven experience taking ICs from first silicon through qualification.

Responsibilities

• Drive end-to-end NPI execution from first silicon through volume production.
• Define reliability and qualification strategies for DSP ICs.
• Lead yield optimization from early silicon through high-volume manufacturing.

Skills

Product engineering

Silicon manufacturing

Reliability engineering

Cross-functional collaboration

Analytical skills

Education

Bachelor’s degree in electrical engineering

Master’s degree preferred

Job description

About The Job

Celero Communications is building next‑generation coherent DSP integrated circuits for high‑performance optical networking. We are seeking a hands‑on, technically deep Principal Product Engineer to drive the transition of Celero’s products from development into qualified, high‑yield, high‑volume manufacturing.

This is a ground‑floor opportunity to work directly within Celero’s engineering and operations teams, playing a critical role in product success while helping establish the operational foundation of a growing semiconductor company. You will define and execute the productization strategy across New Product Introduction (NPI), reliability, test, quality, and manufacturing ramp for advanced coherent DSP ICs delivered as Known Good Die (KGD) and packaged products.

What You Will Do

New Product Introduction (NPI)

• Drive end‑to‑end NPI execution from first silicon through qualification, sampling, and volume production.
• Define NPI milestones, readiness criteria, and exit conditions across design, test, reliability, manufacturing, and operations.
• Work closely with silicon design, DFT, test engineering, supply chain, and operations to ensure manufacturable, testable product launches.
• Identify technical and operational risks early and lead mitigation efforts through data‑driven decision making.

Reliability & Qualification

• Define and execute reliability and qualification strategies for advanced‑node coherent DSP ICs, including Known Good Die (KGD) qualification.
• Develop and own reliability stress plans (HTOL, HTSL, temperature cycling, ESD, latch‑up, early‑life failure, etc.)
• Manage external reliability lab execution, including coverage definition, scheduling, reporting, and failure analysis.
• Analyze qualification data and drive product release readiness based on measured risk and maturity.

Product Quality

• Define internal product quality targets aligned with application and market requirements.
• Own quality metrics related to silicon maturity, yield stability, and manufacturing readiness.
• Drive root‑cause analysis for quality or reliability excursions and lead corrective actions.
• Support customer quality discussions as needed, primarily through preparation of data and technical analysis.

Test, Sampling & Production Ramp

• Lead technical engagement with foundry and OSAT partners from wafer fabrication through back‑end processing and shipment.
• Define and refine production test strategies with test engineering, balancing coverage, cost, yield, and guard‑banding.
• Drive engineering builds, characterization lots, and production ramps.
• Ensuring robust handoff from engineering test flows to stable production manufacturing.

Yield Optimization & High‑Volume Manufacturing

• Own yield learning and yield optimization from early silicon through high‑volume manufacturing.
• Perform deep analysis of wafer sort, die sort, and final test data to identify yield limiters.
• Drive cross‑functional corrective actions across design, process, test, and manufacturing.
• Establish yield targets, dashboards, and regular yield reviews to support sustained volume production.

What You Will Bring

• Bachelor’s degree in electrical engineering or related fields. Master’s degree preferred.
• 10+ years of experience in product engineering, silicon manufacturing, reliability engineering, or related IC lifecycle roles.
• Proven experience taking complex ICs from first silicon through qualification and volume manufacturing.
• Strong background in reliability qualification, stress testing, and failure analysis.
• Experience with wafer‑level test, Known Good Die (KGD), and production test flows.
• Demonstrated success driving yield learning and yield improvement.
• Strong analytical skills and comfort working directly with large manufacturing and test data sets.
• Excellent cross‑functional collaboration skills with a bias toward technical execution.

Why Join Celero

• Be a foundational technical contributor shaping how Celero products scale into manufacturing.
• Deep hands‑on ownership of NPI, reliability, yield, and manufacturing readiness for industry‑defining coherent DSP ICs.
• Opportunity to gain experience technical influence and scope while remaining close to the product and the data.
• High‑impact role in a fast‑moving startup where strong execution directly affects company success.

Salary Range

$150,000 - $250,000 Base Annually

The final offer will be determined based on job‑related skills, experience, qualifications, and location.