Principal Physical Design Engineer, Methodology

Astera Labs; Santa Clara (CA); On-site; USD 185,000 - 240,000; Full time

Job summary

Astera Labs seeks a Principal Physical Design Engineer-Methodology to define, develop, and maintain reusable physical design flows and automation infrastructure. You will own the RTL-to-GDSII flow and coordinate across Cadence and Synopsys toolchains to improve PPA and schedule predictability.

This on-site role is based in San Jose, CA, with responsibilities spanning multi-vendor environments. You will lead automation and scale initiatives, build QoR tracking, and collaborate with IT to optimize

Qualifications

• Bachelor's degree in Electrical or Computer Engineering or related field.
• 8+ years of experience in physical design methodology, CAD, or flow development for complex SoCs at advanced nodes (7nm and below).
• Expert-level scripting in Python, Tcl, or Perl for flow development and automation.
• Experience building and maintaining multi-corner/multi-mode analysis infrastructure.

Responsibilities

• Define, develop, and maintain reusable physical design flows and automation infrastructure across multi-vendor toolchains.
• Own end-to-end RTL-to-GDSII flow infrastructure and improve PPA and schedule predictability.
• Establish best practices, runset standards, and quality checks for multiple tapeout programs; support flow configurations and documentation.

Skills

Python

Tcl

Perl

Flow development

SoC design

Synthesis/Place-and-Route

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree preferred

Tools

Cadence tools (Innovus/Tempus/Voltus/Pegasus)

Synopsys tools (Fusion Compiler/PrimeTime/StarRC/ICC2)

Job description

Principal Physical Design Engineer, Methodology

San Jose, California, United States

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

Role Overview

As a Principal Physical Design Engineer-Methodology , you will define, develop, and maintain the reusable physical design flows and automation infrastructure that the entire PD team relies on. You will build the RTL-to-GDSII flow, integrate and qualify tools from multiple vendors (Cadence and Synopsys), and continuously improve PPA and schedule predictability across all programs. You are the force multiplier scaling the team's capabilities and enabling faster, better tapeouts. This role is fully on-site at our San Jose, CA location.

Key Responsibilities:

• Flow & Methodology Ownership
  • Define, develop, and maintain reusable physical design flows spanning synthesis, place-and-route, extraction, STA, and EMIR
  • Own the end-to-end RTL-to-GDSII flow infrastructure across multi-vendor toolchains (Cadence Innovus, Tempus, Voltus, Pegasus; Synopsys Fusion Compiler, ICC2, PrimeTime, StarRC)
  • Evaluate and qualify new tool features, foundry enablement kits, and flow enhancements to continuously improve PPA and schedule predictability
  • Integrate and maintain DRC/LVS/extraction runsets and ensure consistency with foundry requirements
• Automation & Scale
  • Build and enhance automation scripts and infrastructure to manage large-scale multi-corner/multi-mode STA and EMIR runs with efficient partitioning and resource usage
  • Develop QoR optimization frameworks and tracking methodologies to measure and improve design quality across programs
  • Partner with IT and compute infrastructure teams to optimize job scheduling, storage, and compute resource utilization
• Standards, Quality & Enablement
  • Establish best practices, runset standards, and quality checks that scale across multiple concurrent tapeout programs
  • Support physical design engineers with flow issues, tool configurations, and methodology guidance
  • Drive adoption of flow improvements across the team, including training and documentation

Basic Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Masters Preferred.
• 8+ years of experience in physical design methodology, CAD, or flow development for complex SoCs at advanced nodes (7nm and below)
• Strong knowledge of synthesis, place-and-route, extraction, STA, and equivalence checking flows
• Experience with both Cadence (Innovus, Tempus,Voltus, Pegasus) and Synopsys (Fusion Compiler,PrimeTime,StarRC, ICC2)toolchains
• Expert-level scripting ability in Python,Tcl, and/or Perl for flow development and automation
• Experience building and maintaining multi-corner/multi-mode analysis infrastructure
• Understanding of foundry design rules, technology files, and enablement kit integration
• Ability to work independently with strong prioritization and a results-driven mindset

Preferred Qualifications:

• Knowledge of agentic AI solutions for EDA automation
• Experience with CI/CD integration for physical design flows
• Familiarity with compute farm management and job scheduling optimization
• Knowledge of advanced packaging or multi-die integration flows

The base salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionarybonus, incentives, and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.