Principal NPI Product Engineer

Sierra Wireless; San Diego (CA); Hybrid; USD 78,000 - 99,000; Full time

Benefits offered by this job

Competitive compensation

Hybrid work model

Global team access

Job summary

Semtech's New Product Introduction (NPI) Product Engineering Team is seeking a Principal NPI Product Engineer to own development programs from silicon concept through full production transfer. You will collaborate with design, validation, test, characterization, quality, and operations across CMOS and BiCMOS technologies.

Based in Burlington ON, Bristol UK, or San Diego CA with a hybrid schedule, you will drive DfT/DFM, ATE test programs, and data-driven yield optimization while ensuring on-time

Qualifications

• BS in Electrical Engineering or related field; MS strongly preferred.
• 10+ years in semiconductor product, test or design engineering.
• Ownership of silicon bring-up, characterization, and production transfer.
• Hands-on ATE test development, ATE-to-bench correlation, and test limits.
• Strong DfT and DfM fundamentals.
• Proficiency with JMP/Excel; Python/TCL scripting experience.
• Excellent analytical, problem-solving and cross-functional communication.

Responsibilities

• Drive NPI programs from concept to final release and transfer.
• Define and drive DfT and DfM requirements for NPI products.
• Lead data analysis of ATE and bench characterization across variations.
• Monitor yields, quality metrics, and lead CAPA and continuous improvement.

Skills

Design for Testability (DfT)

Design for Manufacturability (DfM)

ATE test development

Statistical analysis (JMP/Excel)

Python scripting

Cross-functional collaboration

Data analysis

Education

B.S. in Electrical Engineering (MS preferred)

Tools

Advantest/Teradyne platforms

JMP

Job description

Location

Burlington, Ottawa, ON or Bristol, UK (Hybrid – 4 days in office Mon- Thurs)

Our Team

Semtech's New Product Introduction (NPI) Product Engineering Team is the central engineering function behind every new product we bring to market. Our team of focused and talented engineers takes full ownership of new product development — driving each program from conception through end-of-life with a commitment to flawless execution. Working closely with all internal cross-functional teams, our engineers define and drive DfT testability requirements, test coverage, production characterization (across process, voltage, and temperature variations), ATE-to-bench correlation, cost and yield optimization, test time reduction, project logistics, and seamless transfer to full-volume manufacturing. We take pride in delivering high-quality products that exceed customer expectations and drive business success — and our versatile, results-driven team makes it happen.

Job Summary

We are looking for a Principal NPI Product Engineer to take ownership of new product development programs — from early-stage silicon development through full production transfer. Working closely with cross-functional teams across design, validation, test, characterization, quality, and operations, you will be a key technical contributor and program driver for our high-performance optical and analog/mixed-signal IC portfolio in cutting-edge CMOS and BiCMOS technologies.

Key Responsibilities

1. NPI Program Ownership & Cross-Functional Collaboration (25%)

• Drive NPI programs from product concept through final release, ensuring product conformance to specifications and seamless transfer to full-volume manufacturing
• Lead and coordinate with cross-functional teams including Design, Marketing, Validation, Test Engineering, Characterization, Quality & Reliability, Applications Engineering, and Operations
• Own backend NPI development tracking through product transfer; lead milestone reviews of program logistics, timelines, and deliverables
• Prepare and own NPI product release deliverables and OSAT-related manufacturing documentation, ensuring accuracy and completeness

2. Design for Testability & Manufacturability (35%)

• Define and drive Design for Testability (DfT) and Design for Manufacturability (DfM) requirements for NPI products
• Lead development, implementation, verification, and optimization of ATE test programs in collaboration with test engineering
• Drive product characterization, correlation, and release activities to ensure adherence to product specifications and quality standards
• Own finalization of datasheet specifications and ATE production test limits through data-driven, statistically validated limit-setting processes

3. Characterization, Data Analysis & Yield Optimization (30%)

• Develop and own product characterization plans for wafer-level and bench tests across product specifications and operating conditions
• Lead data analysis of ATE and bench characterization results across PVT variations, including ATE-to-bench correlation studies and process capability analysis
• Drive yield modeling activities and lead DOE planning and execution to support yield analysis, test time reduction, and test optimization
• Lead product validation and reliability qualification activities in collaboration with Test, Characterization, Validation, and Reliability Engineering teams
• Identify yield loss Pareto opportunities and drive targeted solutions to closure

4. Manufacturing Quality, Failure Analysis & Continuous Improvement (10%)

• Monitor yields and quality metrics across processing steps; proactively identify and act on trends and anomalies
• Review and own test coverage, test limits, and guard-band decisions
• Lead failure analysis and root cause investigations for field returns and RMA cases; drive CAPA development and closure
• Partner with foundry process and packaging engineering teams to resolve issues during wafer fabrication, packaging, die sort, and final package test
• Identify and implement product lifecycle cost reduction and continuous improvement opportunities

Qualifications

Required

• BS in Electrical Engineering or a related field (MS strongly preferred)
• 10+ years of experience in semiconductor product engineering, test engineering, or design engineering
• Proven ownership of silicon bring-up, characterization, and production transfer programs
• Hands-on experience with ATE test development, ATE-to-bench correlation, and production test limit setting
• Strong foundation in DfT and DfM principles
• Proficiency with statistical analysis tools such as JMP or Excel; scripting/automation in Python, TCL, or equivalent
• Excellent analytical, problem-solving, and cross-functional communication skills

Preferred

• Background in analog/mixed-signal or optical IC characterization (TIA, CDR, LimitAmp, high-speed SerDes)
• Familiarity with high-speed ATE platforms such as Advantest or Teradyne
• Experience with JEDEC reliability qualification methodologies (HTOL, HAST, ESD, latch-up)
• Exposure to ATPG, MBIST, or boundary scan DFT flows
• Experience engaging directly with foundry and OSAT partners

Why Join Semtech

• Work on cutting-edge CMOS and BiCMOS ICs powering next-generation 400G / 800G / 1.6T optical networking infrastructure
• Full program ownership from Day 1 — you drive products, not just support them
• Global, collaborative team with sites in Burlington ON, Bristol UK, Aguascalientes MX, San Diego CA, and an Asia Hub
• Technically rigorous culture with strong cross-functional exposure and direct access to design, reliability, and fab teams
• Competitive compensation, benefits, and professional development opportunities

A reasonable estimate of the pay range for this position is $110,000- $140,000(CAD). There are several factors taken into consideration in determining base salary, including but not limited to: job-related qualifications, skills, education and experience, as well as job location and the value of other elements of an employee’s total compensation package,

The intent of this job description is to describe the major duties and responsibilities performed by incumbents of this job. Incumbents may be required to perform job-related tasks other than those specifically included in this description.

All duties and responsibilities are essential job functions and requirements and are subject to possible modification to reasonably accommodate individuals with disabilities.

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