Principal Engineer, Materials & Thermal Integration

TSMC - Taiwan Semiconductor Manufacturing Company Limited; California; Hybrid; USD 130,000 - 180,000; Full time

Job summary

TSMC Technology, Inc. in San Jose is seeking an R&D Principal Engineer to develop novel materials and integration solutions for advanced semiconductor devices and 3D structures.

You will work hands-on across synthesis, deposition, cleanroom fabrication, and comprehensive characterization to enable next‑generation IC technologies. The role emphasizes collaboration with internal teams in San Jose and Taiwan and university partners, with a hybrid schedule of 4 days in‑office.

Qualifications

• PhD in Physics, Materials Science, Chemistry, Electrical Engineering, or a related field.
• Experience in materials synthesis and thin‑film deposition using CVD, ALD, or PVD.
• Hands‑on cleanroom processing, device fabrication, and characterization techniques.
• Strong knowledge of materials science, surface chemistry, thin‑film growth, etching, planarization, and bonding.

Responsibilities

• Research and develop novel materials and integration solutions for future devices and IC thermal management applications.
• Synthesize and deposit materials using CVD, ALD, PVD, and related techniques.
• Fabricate devices and test structures using cleanroom processes such as lithography, etching, deposition, metallization, and bonding.
• Characterize materials, interfaces, and devices using structural, chemical, electrical, optical, and thermal analysis methods.
• Analyze experimental data and prepare technical reports.
• Collaborate with internal cross‑functional teams and external research partners.
• Conduct research at both in‑house and off‑site facilities.

Skills

Materials science

Independent work

Hands-on lab

Education

PhD in Physics/Materials Science/Chemistry/EE

Tools

CVD

ALD

PVD

Cleanroom

Job description

TSMC Technology, Inc. in San Jose is seeking an R&D Principal Engineer to develop novel materials and integration solutions for advanced semiconductor devices and 3D structures.

You will work hands-on across synthesis, deposition, cleanroom fabrication, and comprehensive characterization to enable next‑generation IC technologies. The role emphasizes collaboration with internal teams in San Jose and Taiwan and university partners, with a hybrid schedule of 4 days in‑office.