Principal Design Verification Engineer (Silicon Engineering)

SpaceX; Palo Alto (CA); On-site; USD 210,000 - 355,000; Full time

Benefits offered by this job

Medical, vision, and dental coverage

401(k) retirement plan

Employee Stock Purchase Plan

Stock options

Job summary

SpaceX in Palo Alto is seeking a Principal Design Verification Engineer (Silicon Engineering) to lead digital ASIC/FPGA verification for space and ground infrastructure. You will design test benches, verification plans, and drive milestones.

The role requires 10+ years in design verification, a bachelor’s in engineering, and expertise in UVM/OVM/VMM, Python scripting, and RTL bring-up. Willingness to work extended hours; competitive compensation.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• 10+ years of design verification and test bench development experience.
• Experience with UVM/OVM/VMM verification methodologies.
• Experience with RTL design, chip bring-up, and post-silicon validation.

Responsibilities

• Lead digital ASIC and/or FPGA verification at block and system level.
• Design and execute verification test plans, develop test benches, and meet milestones.
• Contribute to pre-silicon verification, chip bring-up, and post-silicon validation.
• Act as a self-starter and collaborate with cross-disciplinary teams.

Skills

UVM/OVM/VMM

Test benches

Constrained-random verification

Object-oriented programming

Test plan development

Coverage modeling

RTL design

Chip bring-up

Education

Bachelor's degree in electrical engineering, computer engineering, or computer science

Advanced degree in electrical engineering or computer engineering

Tools

Python

Job description

Position

Principal Design Verification Engineer (Silicon Engineering)

Overview

SpaceX is developing advanced technologies to enable human life on Mars and is expanding Starlink, a global broadband network. We are looking for a motivated engineer to develop next‑generation ASICs for space and ground infrastructure.

Responsibilities

• Lead digital ASIC and/or FPGA verification at block and system level.
• Design and execute verification test plans, develop test benches, and meet milestones.
• Contribute to pre‑silicon verification, chip bring‑up, and post‑silicon validation.
• Act as a self‑starter and collaborate with cross‑disciplinary teams.

Basic Qualifications

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• 10+ years of experience in design verification and test bench development.

Preferred Skills and Experience

• Advanced degree in electrical engineering or computer engineering.
• Experience with UVM/OVM/VMM verification methodologies.
• Strong object‑oriented programming and coding skills.
• Expertise in constrained‑random verification, test plan development, coverage modeling, and results analysis.
• Experience with Python or other scripting languages for automation.
• RTL design, chip bring‑up, and post‑silicon validation experience.
• Ability to adapt to dynamic environments with changing needs.

Additional Requirements

• Willingness to work extended hours and weekends to meet critical milestones.

Compensation & Benefits

• Pay range: $210,000 – $355,000 per year (plus potential long‑term incentives, bonuses, and stock options).
• Comprehensive medical, vision, and dental coverage.
• 401(k) retirement plan.
• Short‑ and long‑term disability insurance, life insurance, paid parental leave.
• Paid vacation (3 weeks) and 10+ paid holidays; 5 days sick leave.
• Employee Stock Purchase Plan.

Legal & Compliance

• ITAR requirements: applicant must be a U.S. citizen, lawful permanent resident, refugee, asylee, or eligible to obtain required U.S. Department of State authorizations.
• Equal Opportunity Employer: SpaceX is an equal opportunity employer and complies with all applicable employment laws.