Principal Design Engineer

Micron Technology, Inc.; San Jose (CA); On-site; USD 140,000 - 298,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid family leave

Robust paid time-off program

Job summary

A leading semiconductor company in San Jose seeks a Principal Design Engineer to innovate in NAND flash memory technology. The role focuses on leading the design and optimization of datapath circuits, incorporating high-speed interfaces, while managing project timelines and mentoring junior engineers. A bachelor's or master's in Electrical Engineering with 8 years of experience and expertise in IO circuit performance is required. Competitive salary ranges from $140,000 to $298,000 annually, with additional benefits.

Qualifications

• 8+ years of relevant IC design experience.
• In-depth knowledge of high-speed IO circuit performance.
• Experience with high-speed interfaces for NAND.

Responsibilities

• Lead the development and optimization of datapath circuits.
• Manage and verify major IO/datapath blocks.
• Collaborate with integration and design teams.

Skills

High-speed IO circuit performance

Power/area optimization

Project management

Physical design flows

Layout optimization

Education

BS or MS in Electrical Engineering

Tools

NAND flash memory

AI applications for design

DRAM interface techniques

Job description

Our vision is to transform how the world uses information to enrich life for all .

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The Principal Design Engineer in Micron’s NVEG organization, you will be at the forefront of shaping the future of memory technology! In this role, you will lead the development, layout, and optimization of ground breaking datapath circuits for next-generation NAND flash memory. You will act as a key technical leader, driving task forces and making strategic architectural decisions to achieve critical design targets such as unprecedented data rates and lower power consumption. By evaluating the trade-offs of emerging architectures, you will advise end-to-end implementation—from design planning and layout to silicon validation—ensuring project achievements are met while mentoring the next generation of engineering talent!

What’s Encouraged Daily:

• Technical Ownership: Manage, design, and verify major IO/datapath blocks (e.g., input receiver, serializer, deserializer, clock distribution, equalizer, ZQ calibration, ONFI training features, and wave pipelines) to strictly meet performance specifications.
• Layout & Optimization: Model layout parasitics and optimize signal quality. Conduct regular layout reviews to identify and complete opportunities for area reduction and power efficiency improvements.
• Multi-functional Integration: Collaborate closely with project integration and other functional design teams to define and negotiate specifications for major block interfaces.
• Silicon Bring-up & Yield: Partner with Product Engineering (PE) to define silicon experiments, drive silicon debugging, and propose architectural fixes to improve yield and performance.
• Customer & Systems Alignment: Liaise with Applications Engineering (Apps) to evaluate the feasibility of introducing new specifications, balancing customer needs against design requirements and physical limitations.
• Document methodologies clearly. Present final results to expert panels and team members. Actively mentor engineers newer to the field to improve the team's technical skills.

Minimum Qualifications

• BS or MS in Electrical Engineering, or a related filed with 8+ years of relevant IC design experience
• 10+ years of in depth knowledge and deep intuitive understanding of high-speed IO circuit performance, power/area optimization, and top level chip architecture/floorplanning.
• Proven track record in physical design flows, layout optimization, and parasitic extraction.
• Demonstrated experience with high-speed interfaces for NAND and sophisticated training/calibration features.
• Strong project management skills with the ability to lead sophisticated design initiatives and effectively communicate progress and outcomes to diverse team members.

Preferred Qualifications

• Hands-on experience in applying AI to improve design quality, workflow efficiency, or layout optimization.
• Experience with DRAM interface(e.g. DDR4/5, LPDDR5/6, HBM3/3E/4) or other high speed industry standard interfaces.
• Experience with signal/power integrity (SI/PI) and chip-level power delivery network(PDN) design and optimization
• Comprehensive understanding of sophisticated CMOS device physics, device reliability mechanisms, BSIM modeling, and CMOS targets for high-speed IO operation.

The US base salary range that Micron Technology estimates it could pay for this full-time position is:

$140,000.00 - $298,000.00 a year

Additional compensation may include benefits, bonuses and equity.

Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits .

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

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To learn more about Micron, please visit micron.com/careers

US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at [e-mail] or 1-800-336-8918 (select option #3)

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.