Principal ASIC Engineer (Reliability & Hardware Validation) Hybrid

Cisco Systems, Inc.; San Jose, Northern (CA, KY); Hybrid; USD 231,000 - 344,000; Full time

Job summary

Cisco Systems, Inc. in San Jose, CA is seeking a senior Hardware Reliability Engineer to lead high-speed design validation and reliability testing for next‑gen semiconductor and networking products.

You will bridge semiconductor testing with board design, ensuring quality, performance, and reliability in hyperscale environments. You will lead qualification activities, collaborate across engineering functions, and drive design-for-reliability from design FMEA to production qualification.

Qualifications

• Master’s degree in electrical engineering or related field.
• 10+ years of professional experience in semiconductor reliability and/or high-speed hardware design.
• Deep knowledge of JEDEC, AEC, and Telcordia standards.

Responsibilities

• Define and execute qualification plans for next-generation high-power solutions (wafer/package level).
• Drive HTOL, Burn-In, and stress testing; manage reliability suppliers and subcontractors.
• Lead hardware design, schematic generation, and validation for service provider routing products; manage board bring-up and debugging.
• Drive failure analysis and generate detailed qualification reports to ensure product integrity.
• Partner with eCAD, FPGA, Power, Mechanical, Signal Integrity, and Manufacturing teams for design-for-reliability and high-speed interface compliance.
• Provide technical documentation and support for customer quality and reliability requirements.

Skills

High-speed design

Semiconductor reliability

HTOL/Burn-In testing

JEDEC/AEC standards

Cadence Allegro

Python/Verilog scripting

Data analysis

Schematic interpretation

Education

Master’s degree in Electrical Engineering

Tools

Cadence Allegro

Job description

The application window is expected to close on: 08/31/2026

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

This role is hybrid in San Jose, California.

Meet The Team

The Cisco Hardware Engineering Team develops and works with Next Generation Technology to build Cisco Hardware products keeping in mind the user experience and in accordance with IEEE standards, and industry best practices. Hardware Engineers serve a range of roles at Cisco from IP Creators and architects creating industry standards, to Solution Integrators driving cross-functional teams to go from concept to production, as well as providing expertise in Solution Verification and ensuring that our products meet Cisco and Industry quality standards. They drive innovation across the large CISCO portfolio, including but not limited to System/Board Design, Circuit Board Layout, Hardware Automation, Validation and Test, Signal Integrity and Power Design. They work multi-functionally with system designers, diagnostics engineers, customer escalation engineers, & external vendors to ensure robust test methodology & timely issue mitigation resulting in high product quality and enable next generation solutions. They drive innovation across Cisco's hardware portfolio and enables next generation solutions through IP development, research, and challenging the status quo within the industry finding ways to optimize cost, performance, and quality.

Your Impact

We are seeking a highly skilled Engineer to lead the reliability and hardware design validation for our next-generation semiconductor and networking products. The ideal candidate will bridge the gap between advanced semiconductor reliability testing and high-speed hardware board design, ensuring our products meet the highest standards of quality, performance, and reliability in hyperscale environments.

You will drive innovation by challenging the status quo, transitioning our reliability approach from traditional methods to ground breaking, industry-leading practices. You will act as a primary technical consultant to business leaders, translating sophisticated engineering challenges into clear business value, and lead multi-functional teams through the entire lifecycle—from design FMEA to production qualification.

Key Responsibilities

• Qualification Strategy: Define and execute comprehensive product/process qualification plans for next-generation, high-power solutions (wafer/package level).
• Reliability Execution: Drive robust, error-free HTOL, Burn-In, and stress testing (HAST, TC, HTS, ESD, LU, SER). Manage reliability suppliers and subcontractors to ensure adherence to qualification schedules.
• Hardware Design & Validation: Lead hardware design, schematic generation, and design validation for service provider routing products. Manage board bring-up and debug processes.
• Failure Analysis: Drive failure analysis activities and generate detailed qualification reports to ensure product integrity.
• Multi-functional Collaboration: Partner with eCAD, FPGA, Power, Mechanical, Signal Integrity, and Manufacturing teams to support design-for-reliability and high-speed interface compliance.
• Customer Support: Provide technical documentation and support for customer quality and reliability requirements.

Minimum Qualifications

• Education: Master’s degree in electrical engineering, Computer Engineering, or a related field.

• Experience: 10+ years of professional experience in semiconductor reliability and/or high-speed hardware design.
• Reliability Expertise: Proven experience in developing high-power HTOL/Burn-In testing for advanced node products. Deep knowledge of JEDEC, AEC, and Telcordia standards.
• Hardware Expertise: Hands‑on experience with high-speed network interfaces, board design, and familiarity with tools such as Cadence Allegro.

• Technical Skills: Experience with high-speed measurement equipment and automated test development. Ability to interpret sophisticated schematics and layouts. Proficiency in data analysis/debug and HTOL set-up

Preferred Qualifications

• Education: PhD in Electrical or Computer Engineering.
• Advanced Node Experience: Experience with 2nm/3nm Hyperscaler Multi-Chip-Modules and advanced packaging (CoWoS, SoIC, EMIB).
• High-Speed Design: Deep expertise in >100Gbps system design, signal integrity, and power distribution. Knowledge of SerDes architecture (NRZ/PAM4 at 56G/112G/224G+), PCIe Gen5/6, and 800G Ethernet.
• Programming: Proficiency in Python, Perl, TCL, or Verilog for scripting and automation.
• Analytical Tools: Experience with JMP, Reliasoft, or Minitab for reliability statistical analysis.
• Methodology: Understanding of FMEA processes, risk assessment, and reliability lifetime modeling.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $231,400.00 to $331,800.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

• 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees

• 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco

• Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees

• Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)

• 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick timecarried forwardfrom one calendar yearto the next

• Additional paid time away may be requested to deal with critical or emergency issues for family members

• Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

• .75% of incentive target for each 1% of revenue attainment up to 50% of quota;

• 1.5% of incentive target for each 1% of attainment between 50% and 75%;

• 1% of incentive target for each 1% of attainment between 75% and 100%; and

• Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:

$231,400.00 - $381,600.00

Non-Metro New York state & Washington state:

$222,900.00 - $343,600.00

* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.