Principal AMS Design Architect: High-Speed SerDes & Optical PHY

Ayar Labs; San Jose (CA); On-site; USD 200,000 - 260,000; Full time

Job summary

Ayar Labs is seeking a Principal Analog/Mixed Signal Design Engineer to shape the architecture of our next-generation co-packaged optics product. You will set the AMS direction across the roadmap and be the technical authority the team relies on for the hardest challenges.

Requirements include a BS in E.E., 12+ years in analog/mixed signal design, and production tapeouts in FinFET CMOS. Proficiency with Cadence ADE and RF/mixed-signal blocks is essential. Base salary range: $200k–$260k.

Qualifications

• 12+ years of industry experience in analog/mixed signal design.
• Track record of production tapeouts in advanced FinFET CMOS nodes.
• Design experience with high speed and high precision analog blocks (PLLs, clock distribution, TX/RX analog front ends, data converters).
• Fluent with Cadence design environment and mixed-signal simulation (ADE, Layout, Spectre).
• Experience driving architectural tradeoff analysis using link budgeting tools.
• Experience designing in FinFET CMOS (7nm or below) at data rates of at least 50Gb/s or RF at 25GHz+.

Responsibilities

• Architect the high-speed optical PHY of the next-generation product.
• Set the AMS technical direction across the roadmap.
• Translate system specs into AMS architecture and block specs.
• Lead the silicon-success methodology and debugging discipline.
• Mentor AMS design engineers in design reviews and silicon debug.
• Drive co-design across the EIC/PIC boundary.
• Represent the AMS organization in cross-functional reviews and discussions.

Skills

Analog/mixed-signal design

Tapeouts

High-speed analog blocks

Architectural tradeoffs

Mentorship

Education

B.S. in Electrical Engineering

MS/PhD in Electrical Engineering

Tools

Cadence

ADE

Spectre

Job description

Ayar Labs is seeking a Principal Analog/Mixed Signal Design Engineer to shape the architecture of our next-generation co-packaged optics product. You will set the AMS direction across the roadmap and be the technical authority the team relies on for the hardest challenges.

Requirements include a BS in E.E., 12+ years in analog/mixed signal design, and production tapeouts in FinFET CMOS. Proficiency with Cadence ADE and RF/mixed-signal blocks is essential. Base salary range: $200k–$260k.