Physical Design Engineer

ZipRecruiter; Milpitas (CA); On-site; USD 100,000 - 140,000; Full time

Job summary

An innovative firm is seeking a skilled Physical Design Engineer with extensive pre-silicon experience. In this dynamic role, you will engage in critical tasks such as Static Timing Analysis, floorplanning, and physical design, ensuring successful ASIC tapeouts. With a focus on collaboration and communication, you will work closely with customers and internal teams to navigate design challenges. If you have a passion for hands-on engineering and a strong background in ASIC Physical Design, this is an exciting opportunity to contribute to cutting-edge projects in a thriving environment.

Qualifications

• 8-10 years of experience in pre-silicon validation and implementation.
• Strong knowledge of ASIC frontend design and layouts.
• Experience with power analysis and physical verification.

Responsibilities

• Perform pre-layout Static Timing Analysis (STA) for feasibility validation.
• Handle chip/block-level floorplanning and clock tree synthesis.
• Engage with customers and integration teams to address design challenges.

Skills

Pre-silicon validation

Implementation

CAD

Block-level design

Communication skills

Problem-solving

Education

BSEE

MSEE

Tools

ICC2

Innovus

Perl

Tcl

Python

PrimePower

Redhawk

Primetime

Job description

Job DescriptionJob DescriptionPhysical Design Engineer

Looking for someone with a wide range of pre-silicon experience. (Example’s) - Validation, Implementation, CAD, Block level. We need someone that has good communication, someone that is hands on and looking to be hands on with broad experience and with 8 + years’ experience with 10 years being the sweet spot.

Overview:
Seeking a hands-on Physical Design Engineer with 8–10 years of experience in pre-silicon validation, implementation, CAD, and block-level design. The ideal candidate will have strong technical expertise, excellent communication skills, and the ability to collaborate closely with customers and internal teams to ensure successful ASIC tapeouts.

Key Responsibilities:
o Perform pre-layout Static Timing Analysis (STA) to validate feasibility and timing constraints.
o Handle chip/block-level floorplanning, pin assignments, and clock tree synthesis (CTS).
o Execute placement, timing optimization, routing, and physical design tasks.
o Conduct sign-off tasks, including RC extraction, IR drop analysis, and physical verification.
o Engage with customers, frontend, and integration teams to address design challenges and ensure smooth execution.
o Present technical findings and participate in customer meetings.

Qualifications:
o BSEE with 5+ years of experience (MSEE ).
o ASIC Physical Design experience, with 28nm/16nm tapeout experience.
o Proficiency in EDA tools (ICC2/Innovus) and scripting (Perl/Tcl/Python).
o Strong knowledge of ASIC frontend design and both flat and hierarchical layouts.
o Experience with power analysis (PrimePower/Redhawk), Static Timing Analysis (Primetime), and Physical Verification.
o Strong problem-solving skills and ability to resolve timing, library, and CAD tool-related issues.
o Excellent communication and customer-facing skills.

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