PCB Layout Engineer, Robotics

Triwill Group; San Francisco, Northern (CA, KY); Hybrid; USD 120,000 - 190,000; Full time

Job summary

OpenAI is seeking a PCB Layout Engineer in San Francisco to design high-density electronics for next-generation robotic systems. You will own the PCB layout from floor planning through fabrication release, collaborating with electrical, SI/PI, mechanical, and manufacturing teams.

The role requires 6+ years of experience with complex multilayer PCBs, Cadence Allegro, and HDI design, including fine-pitch BGAs and via-in-pad. In-person presence four days a week is expected.

Qualifications

• 6+ years of experience designing complex, multilayer PCBs.
• Are fluent in Cadence Allegro PCB Designer and Constraint Manager.
• HDI design experience, including fine-pitch BGAs, microvias, blind and buried vias, via-in-pad, and sequential lamination.
• Understand signal and power integrity fundamentals, including return paths, differential pairs, length matching, crosstalk, and power delivery.
• Have experience working with PCB fabricators on stack-up development, manufacturing constraints, and DFM.
• Communicate effectively across engineering disciplines and with external manufacturing partners.

Responsibilities

• Own PCB layout, component placement, routing, and fabrication release for complex robotic systems.
• Collaborate with SI/PI engineers to refine layouts based on simulation results.
• Implement high-speed routing, controlled impedance, power distribution, decoupling, grounding, EMI/EMC, thermal, and mechanical-integration requirements.
• Work directly with fabricators and assembly partners to define stack-ups, establish design rules, drive DFM/DFA/DFT reviews, and close findings before release.
• Prepare fabrication and assembly documentation, including drawings, ODB++, drill files, stack-up tables, and manufacturing notes.
• Inspect newly received PCBAs and participate in board-level manufacturing failure analysis.
• Contribute to reusable design constraints and layout workflows, and maintain component-library assets such as symbols, footprints, and 3D models.

Skills

6+ years PCB design

HDI design

High-speed routing

Signal integrity

Power integrity

Cross-disciplinary communication

Fine-pitch BGAs

Tools

Cadence Allegro PCB Designer

Constraint Manager

Cadence Sigrity

Ansys SIwave

IPC standards

Cadence SKILL scripting

Job description

Description: About the Team

Our Robotics team is focused on unlocking general-purpose robotics and advancing toward AGI-level intelligence in dynamic, real-world environments. Working across the full model and systems stack, we integrate cutting-edge hardware and software to explore a broad range of robotic form factors. We strive to seamlessly blend high-level AI capabilities with the physical constraints of real-world systems to improve people’s lives.

About the Role

We are looking for a PCB Layout Engineer to design high-density electronics for next-generation robotic systems. You will own PCB layout from floor planning through fabrication release, working closely with electrical, SI/PI, mechanical, and manufacturing teams.

This role is based in San Francisco and requires in-person presence four days per week.

In this role, you will:

• Own PCB layout, component placement, routing, and fabrication release for complex robotic systems.
• Collaborate with SI/PI engineers to refine layouts based on simulation results.
• Implement high-speed routing, controlled impedance, power distribution, decoupling, grounding, EMI/EMC, thermal, and mechanical-integration requirements.
• Work directly with fabricators and assembly partners to define stack-ups, establish design rules, drive DFM/DFA/DFT reviews, and close findings before release.
• Prepare fabrication and assembly documentation, including drawings, ODB++, drill files, stack-up tables, and manufacturing notes.
• Inspect newly received PCBAs and participate in board-level manufacturing failure analysis.
• Contribute to reusable design constraints and layout workflows, and maintain component-library assets such as symbols, footprints, and 3D models.

You might thrive in this role if you:

• Have 6+ years of experience designing complex, multilayer PCBs.
• Are fluent in Cadence Allegro PCB Designer and Constraint Manager.
• Have strong HDI design experience, including fine-pitch BGAs, microvias, blind and buried vias, via-in-pad, and sequential lamination.
• Understand signal and power integrity fundamentals, including return paths, differential pairs, length matching, crosstalk, and power delivery.
• Have experience working with PCB fabricators on stack-up development, manufacturing constraints, and DFM.
• Communicate effectively across engineering disciplines and with external manufacturing partners.

Preferred qualifications:

• Experience with rigid-flex boards or other mechanically constrained designs.
• Experience routing PCIe, DDR, USB, Ethernet, MIPI, or similar high-speed interfaces.
• Familiarity with SI/PI simulation tools such as Cadence Sigrity or Ansys SIwave.
• Experience laying out power supplies or other power-electronics circuits or mixed-signal systems.
• Familiarity with IPC standards, Cadence SKILL scripting, or layout automation.

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic.

For additional information, please see OpenAI’s Aff... https://cdn.openai.com/policies/eeo-policy-statement.pdf.

Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US-based candidates. For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. In addition, job duties require access to secure and protected information technology systems and related data security obligations.

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At OpenAI, we believe artificial intelligence has the potential to help people solve immense global challenges, and we want the upside of AI to be widely shared. Join us in shaping the future of technology.