PCB Layout Engineer

Tenstorrent; Santa Clara (CA); On-site; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a Layout Engineer with expertise in multi-layer PCB layouts for high-performance computing and AI hardware. This role requires direct experience with multi-layer boards, HDI vias, blind vias, back drilling, DFM, DFA and routing / layout of interfaces like GDDR, LPDDR, DDR, PCIe Gen 5 & 6, Ethernet IEEE 802.3bj, cd, cf, USB, etc.

The ideal candidate will work closely with cross-functional teams consisting of engineers from systems, power, signal integrity and mechanical to

Qualifications

• 8+ years in PCB design focusing on high‑performance boards.
• B.S. in EE, CS, or equivalent experience.
• Strong background in high‑speed, complex PCBs (HDI, multi‑lamination, back drilling).
• Experience with layout rules and collaboration with fabricators on stackups and DFM/DFA/DFT feedback.

Responsibilities

• Own multi‑layer PCB layouts for high‑performance computing and AI hardware.
• Route GDDR, LPDDR, DDR, PCIe Gen 5/6, Ethernet, USB and other high‑speed interfaces.
• Proficiency with Cadence schematic/layout tools (v25.1) in Cadence Pulse environment.
• Collaborate with power, signal integrity and mechanical engineers to meet PDN, SI, mechanical, thermal, and regulatory requirements.

Skills

PCB design

HDI vias / multi-layer boards

Cadence Allegro

Altium

High-speed interfaces

Education

Bachelor's degree in Electrical Engineering or Computer Science

Tools

Cadence schematic/layout tools (v25.1)

Cadence Pulse environment

HDI fabrication knowledge

Job description

Tenstorrent is leading the industry on cutting‑edge AI technology, revolutionising performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC‑V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is seeking a Layout Engineer with expertise in board layout for high‑performance computing and AI hardware. This role requires direct experience with multi‑layer boards, HDI vias, blind vias, back drilling, DFM, DFA and routing / layout of interfaces like GDDR, LPDDR, DDR, PCIe Gen 5 & 6, Ethernet IEEE 802.3bj, cd, cf, USB, etc. The ideal candidate will work closely with cross‑functional teams consisting of engineers from systems, power, signal integrity and mechanical to ensure that our products meet the layout margins and cutting‑edge specifications for mass production boards for data centres, workstations, and consumer computing applications.

This role is hybrid, based out of Toronto, ON or Santa Clara, CA.

Who you are

• Experienced board layout engineer with ~8+ years in PCB design (Cadence Allegro; Altium a plus).
• Hold a B.S. in EE, CS, or equivalent experience.
• Strong background in high‑speed, complex PCBs (high layer count, HDI, multi‑lamination, VIPPO, back drilling).
• Comfortable defining and applying layout rules (physical, spacing, length‑matching) for high‑speed designs.
• Confident working with fabricators on stackups, capabilities, and resolving DFM/DFA/DFT feedback.
• Detail‑oriented owner of designs with strong communication skills and the ability to work with an international, cross‑functional team.

What we need

• A Layout Engineer to own multi‑layer PCB layouts for high‑performance computing and AI hardware.
• Expertise routing GDDR, LPDDR, DDR, PCIe Gen 5/6, Ethernet (IEEE 802.3bj/cd/cf), USB and other high‑speed interfaces.
• Proficiency with Cadence schematic/layout tools (v25.1) in the Cadence Pulse environment.
• Ability to choose appropriate advanced fabrication technologies (HDI, blind/buried vias, VIPPO, back drilling) balancing performance and cost.
• Skill in floorplanning, component placement, board connectivity, and creation of power/ground planes.
• Collaboration with power, signal integrity, and mechanical engineers to meet PDN, SI, mechanical, thermal, and regulatory (IPC, UL, CE, RoHS, FCC) requirements.

What you will learn

• How to design boards for cutting‑edge AI and high‑performance computing systems in data centre, workstation, and consumer products.
• Techniques to optimise signal integrity, power delivery, and manufacturability for mass‑production hardware.
• Best practices for working in a deeply cross‑functional environment across systems, power, SI, and mechanical teams.
• Practical experience building around a from‑scratch, high‑performance RISC‑V CPU and AI‑first compute platform.
• How to navigate and integrate global industry and regulatory standards while pushing performance limits.
• The direct impact of your layout work on the roadmap and success of a fast‑growing AI silicon and systems company.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export‑controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.