PCB Engineer

Programmers.io

Dallas (TX)

On-site

USD 90,000 - 130,000

Full time

27 hours ago
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Job summary

Nokia is seeking a skilled PCB Layout Engineer to join our hardware team in Dallas, TX. You will design high-speed, high-density layouts for optical sub-assemblies, and collaborate across electrical and mechanical groups to optimize performance and manufacturability.

You will develop schematic symbols and footprints, manage build files, and contribute to next-generation PCB design technologies while advancing connectivity solutions in a dynamic, innovative environment.

Qualifications

  • BSc in Electrical Engineering or equivalent.
  • Proven PCB layout experience in high-speed/high-density applications.
  • Experience with Cadence CIS and Allegro.
  • Familiarity with fabrication processes, DFM, IPC standards.
  • Strong understanding of signal integrity, power integrity, and thermal management

Responsibilities

  • Execute high-speed, high-density PCB layouts for cutting-edge optical sub-assemblies.
  • Create and manage comprehensive layout and build files, covering PCB design, ceramic and organic substrate designs, and intricate multi-layer packaging.
  • Collaborate closely with electrical and mechanical design teams to establish effective floor planning and PCB constraints, ensuring seamless integration.
  • Work alongside hardware engineers, signal integrity specialists, and mechanical designers to optimize PCB layouts for performance and manufacturability.
  • Develop and maintain schematic symbols and component footprints, streamlining design workflows for maximum efficiency.
  • Complete schematic capture in partnership with the electrical design team, bringing cohesive designs to fruition.
  • Contribute to next-generation PCB design technologies, enhancing your skills while shaping the future of the industry.
  • Tap into robust career development opportunities within a dynamic, innovative environment at Nokia.

Skills

High-speed PCB layout
Signal integrity
Power integrity
Thermal management
Team collaboration

Education

BSc Electrical Engineering

Tools

Cadence CIS
Cadence Allegro

Job description

Collaborating closely with hardware design engineers, you’ll utilize design for manufacturing (DFM) guidelines from our PCB suppliers to ensure functionality and reliability. Your contributions will be vital in advancing unique designs that push the boundaries of technology, paving the way for next-generation innovations. Join us to shape the future of connectivity and technology through iterative development and cutting-edge design solutions.

Your responsibilities
  • Execute high-speed, high-density PCB layouts for cutting-edge optical sub-assemblies, pushing the boundaries of design innovation.
  • Create and manage comprehensive layout and build files, covering PCB design, ceramic and organic substrate designs, and intricate multi-layer packaging.
  • Collaborate closely with electrical and mechanical design teams to establish effective floor planning and PCB constraints, ensuring seamless integration.
  • Work alongside hardware engineers, signal integrity specialists, and mechanical designers to optimize PCB layouts for performance and manufacturability.
  • Develop and maintain schematic symbols and component footprints, streamlining design workflows for maximum efficiency.
  • Complete schematic capture in partnership with the electrical design team, bringing cohesive designs to fruition.
  • Contribute to next-generation PCB design technologies, enhancing your skills while shaping the future of the industry.
  • Tap into robust career development opportunities within a dynamic, innovative environment at Nokia.
Your skills and experience
Must-have:
  • BSc Electrical Engineering Degree or relevant education, training, and experience
  • Proven experience in PCB layout, preferably in high-speed and high-density applications
  • Experience with Cadence CIS and Cadence Allegro
  • Familiarity with PCB fabrication processes, DFM best practices, and IPC standards
  • Strong understanding of signal integrity, power integrity, and thermal management principles
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