Optical Engineer III - Design Analysis

SPECTRAFORCE; Redmond (WA); On-site; USD 103,000 - 110,000; Full time

Job summary

SPECTRAFORCE is seeking an Optical Engineer III - Design Analysis in Redmond, WA to design, simulate, and optimize Photonic Integrated Circuits for visible/IR wavelengths with emphasis on active device integration.

You will generate fabrication-ready layouts, verify PDk compliance, and collaborate across cross-functional teams to tapeout PICs. The role requires MS/Ph.D. and 3+ years of experience in PIC design and photonics.

Qualifications

• MS or Ph.D. in Electrical Engineering, Optical Sciences, Physics, or closely related field.
• 3+ years designing, simulating, and layout of PICs for visible or IR wavelengths.
• Experience with photonic device simulation and EM modeling tools.
• 2+ years with PIC layout tools and GDSII generation; familiarity with foundry PDKs.
• 2+ years of scientific programming (Python or MATLAB).
• 1+ years supporting PIC tapeouts at a commercial foundry.

Responsibilities

• Design, simulate, and optimize PICs and photonic devices.
• Prepare fabrication-ready layouts and ensure PDK compliance.
• Analyze designs with parametric studies and drive design decisions.
• Coordinate design-to-fabrication pipeline with cross-functional teams.

Skills

PIC Design & Simulation

Photonic Modeling Tools

PIC Layout & Tapeout

Python / MATLAB

Education

MS or Ph.D. in Electrical Engineering or Optical Sciences

Tools

Lumerical

Ansys Photonics

Synopsys RSoft

COMSOL

KLayout

Cadence Virtuoso

gdsfactory

Job description

Job Title: Optical Engineer III - Design Analysis

Duration: 24 Months

Location: Onsite in Redmond /WA

Job Description:

Optical Engineer, Photonic Integrated Circuit (PIC) Design & Analysis

• We are seeking a passionate Optical Engineer to join our research and development team. This role focuses on delivering state-of-the-art near-to-eye display system technologies. The ideal candidate will have expertise in novel integrated photonics device design and metrology, gained through a Ph.D. or industry experience.
• Responsibilities
• Design and develop complete Photonic Integrated Circuits (PICs), from fundamental component blocks to full-circuit implementations, with a strong emphasis on active device integration.
• Generate, verify, and prepare fabrication-ready layout files, ensuring compliance with foundry Process Design Kits (PDKs) for external fabrication.
• Conduct systematic design analysis, including optimization and parametric studies, to guide design decisions.
• Support the entire design-to-fabrication pipeline, from initial concept through tapeout, coordinating closely with cross-functional teams and external partners.
• Collaborate with program leadership, Technical Program Managers (TPMs), and researchers on PIC designs that align with overall program objectives.

Must-Have Skills:

• PIC Design & Simulation: 3+ years designing, simulating, and laying out photonic integrated circuits (PICs) for visible/IR wavelengths.
• Photonic Modeling Tools: Proficiency with tools like Lumerical, Ansys Photonics, Synopsys RSoft, or COMSOL for device/circuit analysis.
• PIC Layout & Tapeout: Experience with layout tools (KLayout, Cadence Virtuoso, gdsfactory), GDSII generation, and supporting tapeouts at commercial foundries.

Nice-to-Have Skills:

• Active PIC Design & Validation: Experience in active PIC design, fabrication, and validation, especially for visible wavelengths.
• Device Characterization: Skills in optical/electro-optic measurements, fiber optics, free-space optics, and PIC packaging.
• Statistical Modeling & Sensitivity Analysis: Experience in design space exploration, yield modeling, and incorporating fabrication constraints.

Minimum Qualifications:

• MS or Ph.D. degree in Electrical Engineering, Optical Sciences, Physics, or a closely related field.
• 3+ years of hands-on experience in the design, simulation, and layout of PICs for visible or IR wavelengths on platforms such as Si, SiN, LiNbO, or BTO.
• 3+ years of experience utilizing photonic device simulation and electromagnetic modeling tools for both component and circuit-level analysis (e.g., Lumerical FDTD/MODE/DEVICE, Ansys Photonics, Synopsys RSoft, or COMSOL Multiphysics).
• 2+ years of experience with PIC layout tools and GDSII generation (e.g., KLayout, Cadence Virtuoso, gdsfactory, or equivalent), including familiarity with foundry PDK integration and design rule verification.
• 2+ years of experience with scientific programming (e.g., Python or MATLAB) for scripting, design automation, and analysis.
• 1+ years of experience supporting or executing PIC tapeouts at a commercial semiconductor foundry, including an understanding of fabrication process constraints (e.g., propagation losses, sidewall roughness, etch non-idealities).

Preferred Qualifications:

• 3+ years experience in active PIC design, fabrication, and validation, particularly for visible wavelengths on LiNbO or BTO platforms.
• 3+ years of experience in design space exploration, sensitivity analysis, and statistical performance/yield modeling for photonic circuits.
• 3+ years of experience with one or more major photonic simulation tool suites (e.g., Lumerical, Synopsys, COMSOL, or equivalent).
• 2+ years of experience utilizing photonic circuit-level simulation tools (e.g., Lumerical Interconnect, Synopsys OptSim, or VPIphotonics) for system-level performance evaluation.
• 2+ years of experience in photonic device characterization and test, including both optical and electro-optic measurements.
• 1+ years experience with fiber optics, free-space optics, PIC packaging, and comprehensive device characterization.
• 1+ years experience with semiconductor fabrication processes and a deep understanding of process-induced performance limitations, such as optical losses, sidewall roughness, and process variability.
• Demonstrated ability to directly incorporate fabrication constraints into PIC designs (e.g., optimizing minimum feature sizes and bend radii, implementing effective tapering strategies, and using layout techniques to mitigate scattering and coupling losses).

Minimum Years of Experience: 5-7

Degrees/Certifications:

• Required : MS or Ph.D. degree ( preferred ) in Electrical Engineering, Optical Sciences, Physics, or a closely related field.

Key Projects/Day-to-Day Responsibilities:

• Design, simulate, and optimize PICs and photonic devices.
• Prepare fabrication-ready layouts and ensure compliance with foundry PDKs.
• Analyze and improve designs through parametric studies.
• Coordinate the design-to-fabrication pipeline with cross-functional teams and external partners. Collaborate with leadership and researchers to align designs with program goals.

Purpose/Size of this team & where does this position fit within the team?

• Key technical contributor in the R&D team, collaborating with leadership, TPMs, and researchers. Drives PIC design and fabrication efforts, bridging technical and program objectives.

Certain project that team is working on / what products are they supporting:

• Developing advanced photonic integrated circuits for next-gen near-to-eye display systems. Integrating active devices and optimizing for fabrication constraints. Improving system-level performance and yield through design analysis and modeling.

About the Team:

• R&D team focused on cutting-edge near-to-eye display systems. Multidisciplinary collaboration with engineers, researchers, and program managers. Drives innovation in integrated photonics and display technology.

How will progress be evaluated?

What does success look like for this assignment

• Successful design and tapeout of PICs.
• Quality and innovation in device simulation, layout, and fabrication.
• Effective collaboration and alignment with program goals.
• Ability to optimize designs for performance and manufacturability.

What challenges should the ideal candidate expect in this role, and how can they help address them?

• Overcoming challenges like optical losses, process variability, and device packaging.

What makes this role attractive to top talent, and what unique value does it offer to the ideal candidate?

• Opportunity to work on cutting-edge photonics for next-generation display technology.
• Collaborate with top experts in a highly innovative R&D environment.
• Direct impact on product development and technology advancement.

How many rounds of interviews? 1 round

Types of Interviews:

• 1 round, panel interview with 2-3 interviewers
• Duration: 1 hour
• Focus: Q&A covering diffractive optics, hands-on experimental experience, and discussion of the candidate's PhD work

At SPECTRAFORCE, we are committed to maintaining a workplace that ensures fair compensation and wage transparency in adherence with all applicable state and local laws.This position's pay range is $75.00/hr - $80.00/hr.