NM Process integration and defect reduction yield engineer at INTEL Edgewood, NM

Downtown Boulder Partnership; Edgewood (NM); Hybrid; USD 83,077 - 124,371; Full time

Benefits offered by this job

Hybrid work model

Competitive compensation

Job summary

Intel NM DMO Yield Department seeks engineers to support interconnect and advanced packaging semiconductor fabrication across Fab 11X and Fab 9, including Foveros, EMIB, Die Prep, and Wafer Level Assembly. You will lead experiments, data analysis, and cross-organizational initiatives to optimize processes and yield while improving cost and manufacturability.

Requires problem-solving skills, strong data analysis, and experience in process control.

Qualifications

• Must have a Bachelor's or a Master's degree in chemical engineering, Electrical Engineering, Mechanical Engineering, Material Science, Microelectronics Engineering, Chemistry, Physics or related field.
• This position is not eligible for Intel immigration sponsorship.

Responsibilities

• Plan and conduct experiments and data analysis to optimize and characterize new fabrication processes and understand sources of variation within the fab.
• Control technology change introduction, monitor in line defect and parametric performance and end of line die yields, find root cause for processing excursions and navigate fixes.
• Ensure products are capable of high volume manufacturing while driving improvements to quality, reliability, cost, yield, productivity and manufacturability.

Skills

Creative thinking

Data analysis

Inline detection

Project management

Process control monitoring

Quality event response

Education

Bachelor's degree

Master's degree

Chemical Engineering

Electrical Engineering

Mechanical Engineering

Tools

JMP

SQL

PCS

Job description

Job Description

The NM DMO Yield Department is looking for process integration and defect reduction engineers to support interconnect and advanced packaging semiconductor chip fabrication. Engineers in the NM DMO Yield Department will support Fab 11X and Fab 9 for roles in Foveros, EMIB, Die Prep, Sort, Wafer Level Assembly, and Advanced Packaging. You will partner with all areas of the Yield Department including integration, defect reduction, quality and reliability, device analysis, and yield analysis. Process integration and defect reduction engineers are responsible for sustaining semiconductor fabrication process health on products moving from development to high volume manufacturing while designing and implementing improvements for yield, cost, and defects.

The NM DMO Yield team seeks engineers who enjoy problem solving, data analysis, and leading and participating in cross organizational teams. In this role you will plan and conduct experiments and data analysis to optimize and characterize new fabrication processes and understand sources of variation within the fab. You will be responsible for controlling technology change introduction, monitoring in line defect and parametric performance and end of line die yields, finding root cause for processing excursions and navigating fixes. In addition, yield engineers will receive new products from TD and ensure they are capable of high volume manufacturing while also driving improvement to quality, reliability, cost, yield, productivity and manufacturability.

The following skills are needed to be successful in this role:

• Creative mindset resulting in the ability to propose novel mechanisms and solutions.
• Strong analytical and data analysis skills to identify meaningful correlations and signals in large datasets.
• Understanding of inline detection to identify rogue equipment, identify defect and parametric issues, and predict end of line yield impacts.
• Project management skills to execute roadmaps that drive defect/yield/efficiency/cost improvements based on both known impact and program risk factors.
• Capable of understanding and implementing process control monitoring strategies to detect out of control events which require intervention.
• Can create strong responses to quality events to allow 24/7 disposition during preliminary, ramp, and high-volume stages of product lifecycle.

Full time onsite is required during training (estimated 6 months). After training, hybrid “work from home” to be defined by manager and employee, but continued onsite will be required. Role is not eligible for full time remote work.

Qualifications

Minimum Qualifications:

• Must have a Bachelor's or a Master's degree in chemical engineering, Electrical Engineering, Mechanical Engineering, Material Science, Microelectronics Engineering, Chemistry, Physics or related field.
• This position is not eligible for Intel immigration sponsorship.

Preferred Qualifications:

• Demonstrated capability working in a high performing team culture which includes excellent teamwork and leadership skills, demonstrated problem solving and prioritization skills.
• Fundamental understanding of semiconductor process flow.
• Experience with design of experiments (DOE) principles.
• Experience in high volume manufacturing (HVM).
• Experience in data analysis and statistical process control (JMP, SQL, PCS).
• Understands concepts of statistical process control (SPC), process capability, true spec, and variance.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as benefit programs which include health, retirement, and vacation.

Annual Salary Range for jobs which could be performed in the US $83,077.00-$124,371.00. Salary range dependent on a number of factors including location and experience.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.