Member of Technical Staff: AI Inference Compiler Engineer

Gimlet Labs; San Francisco (CA); Presencial; USD 190.000 - 260.000; Jornada completa

Descripción de la vacante

Gimlet Labs is building the first multi-silicon neocloud designed for fast, efficient AI inference. You will shape compiler infrastructure, optimize how workloads are represented and executed across diverse architectures, and influence scheduling, memory movement, and kernel orchestration for production-scale inference.

This ML-systems–hardware hybrid role focuses on delivering low latency and high throughput by partitioning workloads across devices and by enabling new accelerator architectures

Formación

• Experience building compiler, runtime, or execution infrastructure.
• Experience with IR transformations, compiler passes, lowering, or code generation.
• Strong systems and performance-engineering fundamentals.
• Ability to reason about execution behavior, memory systems, scheduling, and hardware efficiency.
• Strong C++ and/or Python skills.
• A bachelor's degree in a relevant field or equivalent practical experience.

Responsabilidades

• Improve latency, throughput, and efficiency of production inference workloads.
• Design execution strategies for partitioning workloads across heterogeneous hardware.
• Develop compiler optimizations spanning IR transformations, scheduling, memory movement, and kernel orchestration.
• Enable new models, accelerator architectures, and serving techniques to run efficiently in production.

Conocimientos

C++

Python

Compiler infra

Educación

Bachelor's degree in a relevant field

Herramientas

MLIR

LLVM

XLA

TVM

Triton

Descripción del empleo

Gimlet Labs is building the first multi-silicon neocloud designed for fast, efficient AI inference. You will shape compiler infrastructure, optimize how workloads are represented and executed across diverse architectures, and influence scheduling, memory movement, and kernel orchestration for production-scale inference.

This ML-systems–hardware hybrid role focuses on delivering low latency and high throughput by partitioning workloads across devices and by enabling new accelerator architectures