Low-Power RTL Engineer for AI ASICs

Etched; Cupertino (CA); On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

Full medical, dental, and vision packages

Housing subsidy of $2,000/month

Daily lunch and dinner in the office

Relocation support

Job summary

A leading AI hardware company in Cupertino is seeking an experienced RTL Developer to optimize power efficiency in AI chip designs. The ideal candidate will have experience in low-power design using Verilog/SystemVerilog and familiarity with power analysis tools. Competitive benefits include full medical coverage, housing subsidy, and relocation support.

Qualifications

• Experience in RTL development with a focus on low-power design.
• Knowledge in implementing low-power techniques like clock gating.
• Familiarity with synthesis and place-and-route processes.

Responsibilities

• Optimize RTL designs for power efficiency.
• Perform power analysis during silicon design stages.
• Collaborate with physical design team to meet power targets.

Skills

RTL development using Verilog/SystemVerilog

Low-power RTL design

Power analysis tools

Dynamic voltage/frequency scaling (DVFS)

Tools

Synopsys PrimePower

Cadence Joules

Job description

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.

Key responsibilities

• Optimize RTL designs to boost power efficiency while meeting performance and area objectives.
• Perform power analysis throughout various stages of silicon design, applying power-saving strategies in RTL such as clock gating, power gating, multi-voltage domains, and dynamic voltage scaling.
• Conduct power estimation and evaluate PPA trade-offs for both new and existing design features.
• Collaborate closely with the physical design team to ensure power targets are met during the synthesis, place-and-route (P&R), and sign-off phases.
• Create precise power models from RTL simulations and gate-level netlists, and perform power roll-up analysis to estimate chip-level power consumption under different conditions.

You may be a good fit if you have

• Experience in RTL development using Verilog/SystemVerilog, with a focus on low-power RTL design and optimization for complex digital systems.
• In-depth knowledge and experience in implementing low-power techniques like clock gating, power gating, and dynamic voltage/frequency scaling (DVFS).
• Familiarity with synthesis and place-and-route processes with an emphasis on optimizing for power.

Strong candidates may also have experience with

• UPF/CPF power intent specifications.
• Power analysis tools such as Synopsys PrimePower, Cadence Joules, or similar.
• Automation of power analysis and optimization workflows using scripting languages (Tcl, Perl, Python).
• Full medical, dental, and vision packages, with 100% of premium covered
• Housing subsidy of $2,000/month for those living within walking distance of the office
• Daily lunch and dinner in our office
• Relocation support for those moving to Cupertino

How we’re different

Etched believes in the Bitter Lesson . We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

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