Lead Hardware Design Engineer – Power Delivery

Anysilicon; Chandler, Northern (AZ, KY); Hybrid; USD 120,000 - 180,000; Full time

Job summary

PowerLattice Technologies Inc in Chandler, AZ seeks a Lead Hardware Design Engineer - Power Delivery to head the PDN hardware architecture for high-performance chiplet solutions. You will drive schematic entry, PCB layout, and BOM management on multi-layer PCBs, collaborating with SIPI, packaging, and manufacturing teams.

The role requires 10+ years in hardware design, deep PDN knowledge, and strong communication for cross-functional leadership across customers and internal teams.

Qualifications

• 10+ years in hardware design focused on power integrity in high-performance SoCs.
• Hands-on schematic capture and PCB layout using Cadence or Altium.
• Experience with PDN design, power delivery networks, and packaging basics.
• Strong communication and project leadership skills.

Responsibilities

• Lead hardware platforms including schematic entry, PCB layout, and BOM management.
• Drive high-density multi-layer PCB design for PDN.
• Define architectures for reference boards with multi-chiplet SoCs.
• Assist customers in optimizing PDN designs using design kits.
• Lead bring-up and debugging using advanced instruments; mentor teams.

Skills

Power integrity

PCB design

Schematic capture

Mentoring

Cross-functional leadership

Tools

Cadence Allegro

OrCAD

Altium Designer

Job description

Lead Hardware Design Engineer – Power Delivery

PowerLattice Technologies Inc, Chandler, AZ Hybrid work

Job Description:

PowerLattice is a pioneering semiconductor startup focused on revolutionizing high-performance chip power delivery through innovative chiplet solutions. We are seeking a Lead Hardware Design Engineer - Power Delivery to lead the development of our power delivery hardware architecture, ensuring our technology meets the needs of tier-one customers.

Responsibilities:

• Lead the design and development of complex hardware platforms, including schematic entry, PCB layout, and BOM management.


• Drive high-density, multi-layer PCB design focused on Power Delivery Networks (PDN).


• Define hardware architectures for reference platforms and validation boards, integrating multi-chiplet SoC solutions and high-performance power converters.


• Assist customers in optimizing their PDN designs using PowerLattice’s design kits and proprietary chiplet technology.


• Lead the physical bring-up and debugging of complex subsystems, utilizing advanced instrumentation to resolve power/reset timing and silicon anomalies.


• Act as a mentor and project lead, coordinating with cross-functional teams in SIPI, packaging, and manufacturing.

Qualifications:

• 10+ years of experience in hardware design, specifically in power integrity and high-performance SoC platforms.


• Extensive hands-on experience with Schematic Capture and PCB Design tools (e.g., Cadence Allegro, OrCAD, or Altium Designer).


• Deep proficiency in extracting, building, and validating electrical models for SoC packages and power delivery networks.


• Strong understanding of package-level SI/PI, including substrates, interposers, and 2.5D/3D packaging technologies.


• Excellent verbal and written communication skills.

Skills:

• Expertise in hardware design and power integrity.


• Proficient in PCB design tools and methodologies.


• Strong analytical and problem-solving skills in hardware development.


• Ability to mentor and lead cross-functional teams.