Layout Engineering Lead

COHERENT; Sherman (TX); On-site; USD 110,000 - 150,000; Full time

Job summary

Coherent Corp. in Texas is seeking an experienced Senior Layout Engineer to lead physical layout development for III-V laser products including VCSELs, DFB lasers, and related optoelectronic devices.

You will own layout architecture, mask design, and data release from concept through production. The role requires designing production mask sets, developing DRC/LVS automation, and driving layout reviews with process, device, and manufacturing teams.

Qualifications

• Bachelor's, Master's, or Ph.D. in Electrical Engineering, Physics, Materials Science, Optical Engineering, or related field.
• Minimum 5 years of semiconductor layout design experience.
• Minimum 3 years of direct experience with III-V optoelectronic devices such as VCSELs, DFB lasers, edge-emitting lasers, photonic integrated circuits (PICs), or similar.
• Demonstrated experience developing production mask sets and managing layout releases for semiconductor products.
• Experience designing process control monitor (PCM) structures, test keys, and process characterization patterns.
• Strong understanding of semiconductor fabrication processes and how process interactions impact physical layout and device performance.

Responsibilities

• Lead physical layout development for III-V semiconductor laser products including VCSELs, DFB lasers, photonic devices, and related optoelectronic technologies.
• Own layout architecture, mask design, and mask data preparation from concept through production release.
• Develop, maintain, and improve design rule methodologies, verification flows, and layout standards to ensure manufacturable and robust designs.
• Design and implement process monitor structures, test patterns, and characterization vehicles to support process development, process control, yield improvement, and reliability monitoring.
• Develop automated Design Rule Check (DRC), Layout Versus Schematic (LVS), verification, and data analysis solutions using scripting and programming languages such as Python, Tcl, Perl, or equivalent.
• Champion layout automation initiatives to improve design productivity, consistency, quality, and cycle time.
• Collaborate closely with process integration, device engineering, epitaxy, manufacturing, and product engineering teams to ensure layouts meet design, process, reliability, and manufacturing requirements.
• Drive layout reviews and cross-functional design reviews throughout product development and qualification phases.
• Support root cause investigations and failure analysis activities by evaluating potential layout-related issues and implementing corrective actions.
• Establish and maintain layout design guidelines, libraries, reusable cells, and best practices.
• Coordinate mask revisions and change management activities while ensuring configuration control and documentation accuracy.
• Lead multifunctional teams in resolving layout, manufacturability, and process integration challenges.
• Mentor layout engineering techs and provide technical guidance on layout methodologies, DRC compliance, automation, and semiconductor process interactions.

Skills

Semiconductor layout

Python scripting

DRC/LVS automation

Leadership / mentoring

Problem solving

Education

Bachelor's degree in Electrical Engineering

Master's or PhD preferred

Tools

Silvaco layout

Cadence

LVS/DRC tools

Python

C++

Job description

Primary Duties & Responsibilities

• Lead physical layout development for III-V semiconductor laser products including VCSELs, DFB lasers, photonic devices, and related optoelectronic technologies.

• Own layout architecture, mask design, and mask data preparation from concept through production release.

• Develop, maintain, and improve design rule methodologies, verification flows, and layout standards to ensure manufacturable and robust designs.

• Design and implement process monitor structures, test patterns, and characterization vehicles to support process development, process control, yield improvement, and reliability monitoring.

• Develop automated Design Rule Check (DRC), Layout Versus Schematic (LVS), verification, and data analysis solutions using scripting and programming languages such as Python, Tcl, Perl, or equivalent.

• Champion layout automation initiatives to improve design productivity, consistency, quality, and cycle time.

• Collaborate closely with process integration, device engineering, epitaxy, manufacturing, and product engineering teams to ensure layouts meet design, process, reliability, and manufacturing requirements.

• Drive layout reviews and cross-functional design reviews throughout product development and qualification phases.

• Support root cause investigations and failure analysis activities by evaluating potential layout-related issues and implementing corrective actions.

• Establish and maintain layout design guidelines, libraries, reusable cells, and best practices.

• Coordinate mask revisions and change management activities while ensuring configuration control and documentation accuracy.

• Lead multifunctional teams in resolving layout, manufacturability, and process integration challenges.

• Mentor layout engineering techs and provide technical guidance on layout methodologies, DRC compliance, automation, and semiconductor process interactions.

Education & Experience

• Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Physics, Materials Science, Optical Engineering, or a related technical field.

• Minimum 5 years of semiconductor layout design experience required.

• Minimum 3 years of direct experience with III-V optoelectronic devices such as VCSELs, DFB lasers, edge-emitting lasers, photonic integrated circuits (PICs), or similar technologies preferred.

• Demonstrated experience developing production mask sets and managing layout releases for semiconductor products.

• Experience designing process control monitor (PCM) structures, test keys, and process characterization patterns.

• Strong understanding of semiconductor fabrication processes and how process interactions impact physical layout and device performance.

Skills

• Expert-level experience with semiconductor layout tools, preferably Silvaco layout solutions. Experience with equivalent EDA platforms such as Cadence, KLayout, Synopsys, Mentor Graphics/Siemens EDA, or similar tools will also be considered.

• Strong understanding of physical layout design principles, mask design, DRC, LVS, and semiconductor manufacturing constraints.Proficiency in programming and automation using Python, Tcl, Perl, C++, or similar languages.

• Experience developing custom verification tools, automated design rule checks, layout generators, or workflow automation solutions.

• Hands‑on experience with VCSEL, DFB laser, photonic integrated circuit (PIC), or related optoelectronic device layouts.

• Strong knowledge of lithography, etch, metallization, dielectric deposition, implantation, and other semiconductor fabrication processes.

• Familiarity with semiconductor manufacturing operations, process control methodologies, and change management systems.

• Strong analytical and problem‑solving skills with the ability to evaluate complex layout‑process interactions.

• Excellent communication and leadership skills with demonstrated ability to influence and drive actions across multifunctional engineering teams.

• Self‑motivated and capable of leading projects in a fast‑paced product development environment.

• Experience with statistical analysis tools such as JMP, Minitab, or equivalent is a plus.

Working Conditions

• Normal office environment

Physical Requirements

• Work in a class 100/1000 clean room for extended periods
• Wear full cleanroom attire (smock, mask, etc.)
• Work with and/or around chemicals (such as solids and acids)
• Stand for up to 4 hours at a time
• Lift up to 16-30 Pounds
• Push/Pull up to 16-30 pounds
• Sit for up to 4 hours at a time

Safety Requirements

All employees are required to follow the site EHS procedures and Coherent Corp. Corporate EHS standards.

Quality and Environmental Responsibilities

Depending on location, this position may be responsible for the execution and maintenance of the ISO 9000, 9001, 14001 and/or other applicable standards that may apply to the relevant roles and responsibilities within the Quality Management System and Environmental Management System.

Culture Commitment

Ensure adherence to company’s values (ICARE) in all aspects of your position at Coherent Corp.:

I ntegrity – Create an Environment of Trust

C ollaboration – Innovate Through the Sharing of Ideas

A ccountability – Own the Process and the Outcome

R espect – Recognize the Value in Everyone

E nthusiasm – Find a Sense of Purpose in Work

Coherent Corp. is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.

If you need assistance or an accommodation due to a disability, you may contact us at [e-mail] .

ABOUT US

Coherent is a global leader in lasers, engineered materials and networking components. We are a vertically integrated manufacturing company that develops innovative products for diversified applications in the industrial, optical communications, military, life sciences, semiconductor equipment, and consumer markets. Coherent provides a comprehensive career development platform within an environment that challenges employees to perform at their best, while rewarding excellence and hard‑work through a competitive compensation program. It's an exciting opportunity to work for a company that offers stability, longevity and growth. Come Join Us!

Pay Scale

$0.00 - $0.00 per [frequency]