Kernel Engineer

Acceler8 Talent; San Francisco (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

Acceler8 Talent in the San Francisco Bay Area is seeking a Kernel Engineer to advance accelerator performance on NVIDIA GPUs using CUDA. You will own low-level kernels, profile workloads, and push memory and compute balance for real-world autonomous systems.

You will explain bottlenecks, implement variants, and collaborate with neighboring teams to apply rapid, measurable improvements. A hands-on, problem-solving mindset and deep hardware intuition are essential.

Qualifications

• Hands-on authorship or substantial optimization of accelerator kernels.
• Strong computer architecture fundamentals and detailed reasoning about memory hierarchy and execution behavior.
• Ability to explain your own code-level changes and support performance claims with credible measurements.
• Independent problem solving, strong debugging skills and a preference for hands-on engineering.
• Ability to connect an observed performance problem to a hardware constraint and explain why a particular implementation change addresses it.
• Practical understanding of bandwidth, execution scheduling, memory hierarchy and register use, supported by personal engineering examples.
• A disciplined approach to measurement and debugging, including investigating new bottlenecks after an optimization.

Responsibilities

• Author or materially optimize accelerator kernels, using the current NVIDIA and CUDA stack.
• Profile workloads and identify bottlenecks in memory access, execution, bandwidth and scheduling.
• Tune data movement, register use and parallel execution to make better use of accelerator resources.
• Validate correctness and quantify performance improvements under representative conditions.
• Investigate how bottlenecks change after an optimization and use the results to guide further work.
• Collaborate with adjacent engineering teams to apply low-level improvements within larger compute workloads.
• Establish a representative performance baseline and use profiling to distinguish compute limits from memory-bandwidth, scheduling or synchronization constraints.
• Examine memory layout, access patterns, register pressure and work distribution to identify the most effective low-level change.
• Implement and compare kernel variants, explaining the trade-offs between data movement, parallelism and hardware resource use.
• Use appropriate reference results and representative inputs to check numerical behavior and maintain correctness while improving performance.
• Communicate both the measured improvement and its operating conditions so other engineers can integrate the work effectively.

Skills

Kernel optimization

CUDA profiling

Memory hierarchy

Performance measurements

Low-level debugging

Tools

CUDA

Job description

Kernel Engineer

GPU performance for physical AI and robotics | San Francisco Bay Area

The opportunity

Acceler8 Talent is partnering with a stealth robotics and manufacturing startup developing autonomous systems for real-world production. The team is hiring a Kernel Engineer to improve accelerator performance through deep understanding of hardware architecture and direct ownership of low-level implementation.

You will turn profiling evidence into kernel changes, working through memory hierarchy, bandwidth, scheduling and execution constraints. The role suits engineers who can explain why an operation is slow, which hardware limit dominates and how their changes improve the workload.

Technical scope

The current implementation environment uses NVIDIA GPUs and CUDA. The technical emphasis is on understanding accelerator behavior deeply enough to change how an operation executes, rather than relying only on library selection or high-level configuration. You will work through data reuse, memory traffic, parallel scheduling and resource limits, then evaluate how those decisions affect the larger workload used by adjacent engineering teams.

What you will do

• Author or materially optimize accelerator kernels, using the current NVIDIA and CUDA stack.
• Profile workloads and identify bottlenecks in memory access, execution, bandwidth and scheduling.
• Tune data movement, register use and parallel execution to make better use of accelerator resources.
• Validate correctness and quantify performance improvements under representative conditions.
• Investigate how bottlenecks change after an optimization and use the results to guide further work.
• Collaborate with adjacent engineering teams to apply low-level improvements within larger compute workloads.
• Establish a representative performance baseline and use profiling to distinguish compute limits from memory-bandwidth, scheduling or synchronization constraints.
• Examine memory layout, access patterns, register pressure and work distribution to identify the most effective low-level change.
• Implement and compare kernel variants, explaining the trade-offs between data movement, parallelism and hardware resource use.
• Use appropriate reference results and representative inputs to check numerical behavior and maintain correctness while improving performance.
• Communicate both the measured improvement and its operating conditions so other engineers can integrate the work effectively.

What you will bring

• Hands-on authorship or substantial optimization of accelerator kernels.
• Strong computer architecture fundamentals and detailed reasoning about memory hierarchy and execution behavior.
• Ability to explain your own code-level changes and support performance claims with credible measurements.
• Independent problem solving, strong debugging skills and a preference for hands-on engineering.
• Ability to connect an observed performance problem to a hardware constraint and explain why a particular implementation change addresses it.
• Practical understanding of bandwidth, execution scheduling, memory hierarchy and register use, supported by personal engineering examples.
• A disciplined approach to measurement and debugging, including investigating new bottlenecks after an optimization.

Useful experience

• Deep NVIDIA GPU and CUDA optimization experience with authored or substantially modified kernels.
• TPU, JAX or other accelerator experience when supported by comparable architecture and implementation depth.
• Embedded inference, compiler or simulation-performance work involving direct low-level optimization.
• Seniority is flexible, including strong early-career engineers with substantial kernel projects and experienced engineers with demonstrated independent ownership.