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Ayar Labs, the global leader in optical I/O chiplets, invites undergraduates or graduates to join the Link Architecture team as an Intern for Statistical Analysis & Modeling. You will develop statistical device models and system simulations, bridge simulation to measurement, and correlate device measurements to models.
Mentorship provided by a senior engineer. This on-site internship in San Jose offers hands-on experience in co-packaged optics, data-driven modeling, and collaboration with design
Position: Intern, Link Modeling/Architecture - Statistical Analysis & Modeling
Location: San Jose, CA
Job Id: 765
# of Openings: 0
Term: May to August 2027
Please note:
Ayar Labs, the global leader in optical I/O chiplets, is harnessing silicon photonics to revolutionize the scaling of AI compute hardware. Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.
Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.
We are looking for motivated undergraduate or graduate interns to join our Link Architecture team, where you will develop statistical device models and system simulations that bridge the gap between simulation and measurement. In this role, you will collaborate with design and test teams to correlate device measurements to device models and system level simulations. Projects are tailored to your experience and interests, and you will be mentored by a senior engineer as you work alongside with Ayar Labs engineers to help drive the optical I/O revolution.
Pay Range: $50 - 60/hourly, depending on education level
Ayar Labs is an Affim-