Interface Design Architect, HBM - DMTS

Micron; Richardson (TX); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Medical benefits

Dental benefits

Vision plan

Paid time off

Job summary

Micron Technology is seeking a senior memory interface engineer to own HBM IO blocks from architecture through silicon bring-up and post-silicon debugging. You will define HBM PHYs, die-to-die interfaces, and training/calibration strategies for high-speed memory subsystems.

You will lead architecture and design of analog, mixed-signal, and digital interfaces and work with packaging, SI/PI, and thermal teams to optimize performance. A strong background in RTL/verification is required.

Qualifications

• 18+ years of experience in memory/interfaces or related IC design roles.
• Experience delivering complex interface IP from architecture to post-silicon debug.
• Strong expertise in high-speed memory-interface architecture and design.

Responsibilities

• Own and deliver critical HBM IO blocks and subsystems from architectural definition through silicon bring-up and post-silicon debug.
• Define HBM PHY, controller-to-PHY, die-to-die interfaces, clocking, training, calibration, power-management, and test requirements.
• Lead architecture and design of analog, mixed-signal, and digital interface functions for high-speed memory subsystems.
• Mentor engineers through architecture and build reviews and improve IP reuse and execution rigor.

Skills

HBM Architecture

High-speed memory

RTL design

Analog & mixed-signal

Technical leadership

Front-end verification

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Verilog

SystemVerilog

HSPICE

FastSPICE

Job description

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Responsibilities will include, but are not limited to:

• Own and deliver critical HBM IO blocks and subsystems from architectural definition through circuit and RTL implementation, verification, tape-out, silicon bring-up, and post-silicon debug, including interfaces supporting future CPO systems.
• Define HBM PHY, controller-to-PHY, die-to-die, clocking, training, calibration, power-management, error-handling, and test requirements for advanced heterogeneous systems.
• Drive robust, high-performance builds by balancing bandwidth, latency, power, area, reliability, electrical signal quality, power stability, yield, and manufacturability trade-offs.
• Lead architecture and design of analog, mixed-signal, and digital interface functions used in high-speed memory subsystems.
• Partner with package, interposer, physical design, signal integrity, power integrity, and thermal teams to optimize interface implementation across 2.5D and 3D systems.
• Lead root-cause analysis and resolution of complex pre-silicon and post-silicon issues across circuit design, RTL, architecture, process, package, interposer, and system interactions.
• Serve as technical project lead for one or more advanced interface programs, coordinating execution across architecture, design, layout, verification, validation, packaging, test, and product engineering teams.
• Define and communicate technical priorities, interface specifications, execution plans, risks, dependencies, and schedule impacts.
• Work with internal teams, customers, IP providers, foundries, and ecosystem partners to define and integrate high-speed memory and die-to-die interface solutions.
• Research, develop, and influence next-generation HBM, CPO, chiplet, and heterogeneous-integration architectures aligned with artificial intelligence, machine learning, and high-performance computing workloads.
• Apply deep knowledge of DRAM operation, HBM and DDR interfaces, JEDEC specifications, mixed-signal design, memory subsystems, and high-speed interfaces to architect scalable solutions.
• Mentor engineers through architecture reviews, build reviews, and hands-on problem-solving while improving build methods, guidelines, IP reuse, and execution rigor.

Minimum Qualifications:

• 18+ years of experience in HBM, DDR, LPDDR, advanced memory, high-speed PHY, mixed-signal design, system-on-chip, or application-specific integrated circuit design roles.
• Proven experience delivering complex interface IP or subsystems from architecture through silicon bring-up and post-silicon debug.
• Strong expertise in high-speed memory-interface architecture and design, preferably including HBM product families.
• Extensive experience with analog and mixed-signal circuit design, digital microarchitecture, RTL design, clocking, training, calibration, power management, and error handling.
• Experience with front-end implementation and verification, including synthesis, static timing analysis, logic equivalence, and RTL debug.
• Demonstrated technical project leadership across multidisciplinary and multi-site engineering teams.
• Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or a related field.

Preferred Qualifications:

• Direct experience architecting or developing HBM PHYs, DDR or LPDDR PHYs, or complete PHY and controller subsystems.
• Experience with CPO system architecture, optical-engine electrical interfaces, silicon-photonics integration, or high-speed SerDes.
• Experience with UCIe or other die-to-die interfaces and chiplet-based architectures.
• Experience with transistor-level design and analog simulation tools such as FastSPICE, HSPICE, or similar.
• Experience with digital design using Verilog, SystemVerilog, or similar RTL methodologies.
• Exposure to 2.5D or 3D packaging technologies, including through-silicon vias, microbumps, hybrid bonding, and interposers.
• Experience with signal integrity, power integrity, package electrical design, and high-speed channel analysis.
• Experience integrating external IP into complex SoCs or heterogeneous multi-die systems.
• Experience contributing to JEDEC, DFI, UCIe Consortium, OIF, or other relevant technical standards.
• Strong communication skills, with the ability to explain complex technical concepts to engineers, leaders, customers, and ecosystem partners.
• Demonstrated innovation through patents, technical publications, standards contributions, or successful introduction of new interface technologies.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth.

Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

To learn more about Micron, please visit micron.com/careers.

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.