IC Design Intern - CMOS, AI & Submicron Circuits

IBM; Town of Yorktown (NY); On-site; USD 89,000 - 164,000; Full time

Benefits offered by this job

Paid holidays

Stock Purchase Plan

Family medical leave

Job summary

IBM Research in Yorktown Heights, NY, is seeking an Intern/Co-op to contribute to innovative integrated circuits in deep submicron CMOS for AI acceleration and high-speed communications. You will join a world-class team of engineers and researchers to design, verify, and document digital and mixed-signal building blocks along with architecture decisions.

Responsibilities include co-simulation, verification, and supporting physical design, with opportunities to learn from leaders in IC design and

Qualifications

• Bachelor's degree required; Master's degree preferred.
• Experience with IC development tools (Cadence) and deep sub-micron CMOS technologies.
• Proven ability to complete complex mixed-signal and/or digital IC designs.
• Ability to communicate technical ideas effectively.

Responsibilities

• Collaborate on architecture/system-level development using simulations and data analysis.
• Design and synthesis of digital and mixed-signal circuit blocks to meet specs.
• Co-simulation and verification of circuits and subsystems.
• Support physical design/synthesis and post-layout verification.
• Document design concepts, simulations, and verification results.

Skills

IC design

System-level design

Digital & Mixed-signal design

Verifications

Education

Bachelor's Degree

Master's Degree

Tools

Cadence

Job description

IBM Research in Yorktown Heights, NY, is seeking an Intern/Co-op to contribute to innovative integrated circuits in deep submicron CMOS for AI acceleration and high-speed communications. You will join a world-class team of engineers and researchers to design, verify, and document digital and mixed-signal building blocks along with architecture decisions.

Responsibilities include co-simulation, verification, and supporting physical design, with opportunities to learn from leaders in IC design and