High-Performance ML Inference Engineer (Hybrid)

Long Ridge Partners; New York (NY); On-site; USD 600,000 - 1,500,000; Full time

Benefits offered by this job

Hybrid working options

Free meals (breakfast, lunch)

Wellness reimbursement

Regular social events

Learning opportunities

Job summary

Long Ridge Partners is seeking a Machine Learning Performance Engineer (Inference) to architect ultra-low-latency inference pipelines for high-frequency trading. You will benchmark workloads across CPU, GPU, and FPGA, drive hardware architecture decisions, and deploy optimized kernels and libraries to maximize throughput and reduce latency in production.

The role focuses on end-to-end performance, including memory hierarchies, interconnects, and thermal/power constraints, with cross-functional

Qualifications

• 2+ years optimizing deep learning inference in latency-sensitive or high-throughput production environments.
• Strong Python and C++ skills with understanding of mixed-precision computation.
• Experience in lower-level ML framework development (PyTorch/JAX) and kernel optimization.
• Experience building GPU kernels and using optimization libraries and profilers.

Responsibilities

• Architect and optimize inference pipelines for microsecond-latency trading workloads.
• Benchmark workloads across CPU/GPU/FPGA and guide hardware deployment decisions.
• Develop highly optimized kernels and integrate performance libraries.
• Collaborate with ML researchers, HPC/FPGA/datacenter engineers to productionize deployments.

Skills

Python

C++

PyTorch/JAX

mixed-precision computation

kernel development

profiling

Tools

Triton

TensorRT

ONNX

IREE

HLS4ML

cuBLAS

CUTLASS

Nsight Systems

Nsight Compute

Job description

Long Ridge Partners is seeking a Machine Learning Performance Engineer (Inference) to architect ultra-low-latency inference pipelines for high-frequency trading. You will benchmark workloads across CPU, GPU, and FPGA, drive hardware architecture decisions, and deploy optimized kernels and libraries to maximize throughput and reduce latency in production.

The role focuses on end-to-end performance, including memory hierarchies, interconnects, and thermal/power constraints, with cross-functional