Head of Silicon Product Engineering

Normal Computing Corp.; Mountain View (CA); On-site; USD 300,000 - 420,000; Full time

Job summary

Normal Computing is seeking a Head of Silicon Product Engineering in Mountain View, CA to own end-to-end bring-up, characterization, validation, and debug across multiple silicon generations. You will define packaging and test strategies, manage OSAT and test-house partnerships, and drive yield improvements for memory products.

You will build and lead a high-performance silicon product engineering organization from the ground up, set test/calibration methodologies, and collaborate with design,

Job description

Normal Computing | Build with Us

Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.

The Role

Normal builds custom silicon for AI inference. As Head of Silicon Product Engineering, you will own everything that happens between a design being correct and a product being real: packaging, test and ATE, post-silicon validation and bring-up, yield and qualification, OSAT and test-house selection, and production calibration and screening of our memory products.

This is a build role. You will stand up the team, the vendor relationships, and the processes that take Normal’s silicon from tape-out through high-volume manufacturing, working at the intersection of design, manufacturing, and product to turn architectural intent into a producible, testable, reliable product at scale. You will also be setting precedent: establishing test and calibration methodology for a new silicon program as it m

What You Will Own

• Post-Silicon Strategy: Own end-to-end bring-up, characterization, validation, and debug across multiple silicon generations.

• Packaging & Test: Define and drive packaging and test strategy, including ATE program development, test coverage, and test condition optimization for yield, quality, and performance.

• OSAT & Test-House Selection: Select, qualify, and manage OSAT and test-house partners; own the relationship through NPI and into high-volume manufacturing, including cost, quality, and yield negotiations.

• Yield & Qualification: Lead yield learning and qualification efforts from early silicon through production ramp, including root-cause analysis of systematic and random failures.

• Production Calibration & Screening: Own production calibration and screening methodology for our memory products, ensuring performance and reliability targets are met at volume.

• Team Build: Build and lead a high-performing silicon product engineering organization from the ground up, including hiring, process, and tooling.

• Cross-Functional Feasibility: Partner closely with design, architecture, and supply chain teams to ensure designs are producible, testable, and optimized for cost and yield before they become expensive to change.

• Data Infrastructure: Build the data analysis practices needed to catch failure mechanisms early: characterization and manufacturing data from wafer acceptance testing, sort, package, and system-level test.

What Makes You a Great Fit

• 15+ years in semiconductor product/test engineering, with direct ownership of silicon from NPI through high-volume manufacturing.

• Proven experience selecting and managing OSAT and foundry partners, including cost, quality, and yield negotiations.

• Deep hands-on background in packaging, ATE, and post-silicon bring-up and validation.

• Experience with production test and screening methodology for complex, high-reliability products.

• A track record of building and scaling engineering teams from early stage.

• Strong cross-functional fluency with design, architecture, and supply chain organizations.

• Bachelor’s or Master’s degree in Electrical Engineering or a related field.

Bonus Points

• Experience bringing up test and qualification for a new or unconventional silicon architecture, not just a new generation of a familiar one.

• Experience with memory-adjacent product engineering (DRAM, HBM, or custom memory modules).

• Experience at an AI or high-performance compute startup where design, verification, and product engineering worked in tight iteration cycles.

• Comfort operating in an environment where the test methodology is still being invented alongside the hardware.

Equal Employment Opportunity Statement

Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.

Accessibility Accommodations

Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at [e-mail].

Privacy Notice

By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Applicant Privacy Notice.