Hardware Engineer

femtoAI; San Bruno (CA); On-site; Full time

Benefits offered by this job

401(k)

Medical insurance

Vision insurance

Disability insurance

Paid maternity leave

Paid paternity leave

Child care support

Job summary

A leading AI technology firm is seeking a Hardware Engineer to join their hardware team in San Bruno, California. The role involves designing and building neural network accelerators and contributing to RTL design and implementation. Candidates should demonstrate proficiency in HDL languages like SystemVerilog and have a strong foundation in digital design. The position offers competitive benefits including medical and disability insurance, as well as paid parental leave.

Qualifications

• Experience or coursework involving RTL design and microarchitecture.
• Knowledge of physical design and verification.
• Interest in or exposure to machine learning accelerators.

Responsibilities

• Design and implement RTL for components of a neural network accelerator.
• Translate architectural specifications into efficient hardware implementations.
• Collaborate with hardware architects to ensure functional correctness.

Skills

Proficiency in HDL languages like SystemVerilog and/or VHDL

Strong foundation in digital design

Proficiency in Python for scripting and automation

Strong technical communication skills

Education

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field

Tools

UVM design verification frameworks

Job description

San Bruno, United States | Posted on 02/13/2026

• Work Experience Current Student / Recent Grad
• City San Bruno
• State/Province California
• Country United States

About Us

Headquartered in Silicon Valley, femtoAI—formerly known as Femtosense—was founded in 2018 by researchers from the Brains in Silicon Lab at Stanford University. Our technology takes inspiration from the principles of neuromorphic computing such as sparsity to empower intelligence in everyday devices.

We pioneered a high-performance AI accelerator integrated with an end-to-end embedded AI platform, enabling low-latency operation with less energy at a fraction of the cost. From wearables and household appliances to robotics and autonomous vehicles, femtoAI brings the power of AI to everyday devices.

Job Description

As a Hardware Engineer, you will join femtoAI’s hardware team to help design and build our novel neural network accelerator. Working in a small, highly collaborative group, you will contribute directly to RTL design, microarchitecture implementation, and functional correctness of core hardware blocks.

Depending on your interests and strengths, your work may emphasize RTL development, design verification, or both, with opportunities to grow into deeper specialization over time. You will also gain exposure to the broader hardware development lifecycle, including verification infrastructure and backend design considerations.

Responsibilities

• Design and implement RTL for components of a neural network accelerator
• Translate architectural specifications into efficient, maintainable hardware implementations
• Collaborate with hardware architects and verification engineers to ensure functional correctness and performance targets
• Write tests, assertions, or simple verification environments to validate your designs
• Contribute to improving internal hardware design and verification workflows using scripting and automation
• Participate in design reviews, debugging, and bring-up of new hardware blocks

Requirements

• The candidate must have:
• Proficiency in HDL languages like SystemVerilog and/or VHDL
• Strong foundation in digital design, computer architecture, and VLSI through coursework or projects
• Familiarity with ASIC or FPGA design flows
• Proficiency in Python for scripting and automation
• Strong technical communication skills and ability to collaborate across disciplines
• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field
• The ideal candidate will also have:
• Experience or coursework involving RTL design and microarchitecture
• Proficiency with UVM design verification frameworks
• Knowledge of physical design and verification
• Experience or coursework related to on-chip interconnects
• Interest in or exposure to machine learning accelerators
• 401(k)
• Medical insurance
• Vision insurance
• Disability insurance
• Paid maternity leave
• Paid paternity leave
• Child care support

femtoAI is an equal opportunity employer committed to a diverse workforce which strives to create an inclusive working environment empowering everyone to do their best work. We do not discriminate on the basis of race, ethnicity, religion, gender, gender identity, sexual orientation, age, marital status, veteran status, or disability status.