Hands-on Hardware ASIC Design Internship

NVIDIA Corporation; Santa Clara (CA); Sur place; USD 28 000 - 98 000; Plein temps

Avantages offerts par ce poste

Intern benefits

Résumé du poste

NVIDIA Corporation in Santa Clara, CA offers a 12-week full-time internship for students pursuing a B.S., M.S., or Ph.D. in Electrical or Computer Engineering.

You will work on projects with measurable impact across RTL design, HDL, VLSI, computer architecture, and system software tools. This paid internship provides hands-on experience on industry-leading hardware teams, with collaboration across hardware and software disciplines and exposure to performance optimization and verification

Qualifications

• Actively enrolled in university for full internship duration with clearly indicated graduation date on resume/CV.
• Course/internship experience in RTL design, HDL, VLSI, or related fields may be required.
• Programming skills in SystemVerilog/Verilog, C, C++, Python; familiarity with Linux environment.

Responsabilités

• Contribute to 12-week internship projects with measurable business impact.
• Collaborate with hardware and software teams on design, verification, and performance optimization.
• Develop testbenches, perform timing analysis, and contribute to P&R and timing closure tasks.

Connaissances

RTL Design

HDL

Digital Systems

VLSI Design

Computer Architecture

Object-Oriented Programming

C/C++

Python

Linux

SystemVerilog/Verilog

UVM

Formation

Pursuing B.S./M.S./Ph.D. in Electrical Engineering or Computer Engineering

Outils

Testbench Tools

Verilog/VHDL Tools

Description du poste

NVIDIA Corporation in Santa Clara, CA offers a 12-week full-time internship for students pursuing a B.S., M.S., or Ph.D. in Electrical or Computer Engineering.

You will work on projects with measurable impact across RTL design, HDL, VLSI, computer architecture, and system software tools. This paid internship provides hands-on experience on industry-leading hardware teams, with collaboration across hardware and software disciplines and exposure to performance optimization and verification