FPGA Engineer II

Socket.dev; Plano (TX); On-site; USD 69,000 - 131,000; Full time

Job summary

RTX in Plano, TX is seeking an FPGA Engineer II to develop FPGA designs for AMD (Xilinx), Altera, and Microchip devices. You will code in VHDL/Verilog, verify with constrained tests, and collaborate with systems engineers from requirements to production release.

The role requires a DoD Top Secret clearance and U.S. citizenship. Onsite work in Plano, TX and a strong background in FPGA/ASIC design with lab experience are essential.

Qualifications

• Typically requires a STEM degree with a minimum of 2 years of relevant experience.
• Experience with FPGA/ASIC design or verification (VHDL/Verilog or SystemVerilog).
• Hands-on lab integration and debugging of FPGA/ASIC devices.
• Experience with AMD (Xilinx), Altera and/or Microchip devices and tools (Vivado/Quartus/Libero).
• Git, code reviews, and team-based release processes.

Responsibilities

• Provide full lifecycle support of production-quality FPGA designs for major vendors/devices.
• Generate FPGA designs for multi-gigabit interfaces, RF DSP, controls, and embedded processing.
• Assist with architecture development of FPGA-based systems and CONOPS.
• Code in VHDL for reliability and maintainability.
• Support design verification with directed and constrained tests and track coverage.
• Report execution status within budget/schedule using an agile framework.
• Create documentation including requirements, verification plan, and user guides.
• Engage as an individual contributor and present work to leadership.

Skills

FPGA design

VHDL/Verilog

SystemVerilog

Git

Python/C

CI/CD

Questa/RivieraPro

Education

STEM degree

Tools

Vivado

Quartus Pro

Libero

Questa

RivieraPro

Git

Job description

Date Posted:

2026-09-18

Country:

United States of America

Location:

US-TX-PLANO-465 ~ 465 Independence Pkwy ~ INDEPENDENCE

Position Role Type:

Onsite

U.S. Citizen, U.S. Person, or Immigration Status Requirements:

The ability to obtain and maintain a U.S. government issued security clearance is required. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance

Security Clearance Type:

DoD Clearance: Top Secret

Security Clearance Status:

Active and existing security clearance required after day 1

At Raytheon, the foundation of everything we do is rooted in our values and a higher calling – to help our nation and allies defend freedoms and deter aggression. We bring the strength of more than 100 years of experience and renowned engineering expertise to meet the needs of today’s mission and stay ahead of tomorrow’s threat. Our team solves tough, meaningful problems that create a safer, more secure world.

In this role as an FPGA Engineer II, you will be supporting a development program within the Airborne RF Electronics Design Department. You will develop FPGA designs for all major vendors and device families including AMD, Altera, and Microchip. Designs commonly support the following applications: multi-gigabit interfaces, Radio Frequency (RF) and Electro-Optical (EO) DSP, controls, data links, embedded processing, and processor interfaces. Designers collaborate with circuit card designers and systems engineers to develop requirements, architecture, modeling of algorithms, partitioning, code development, simulation, and place and route. Designs are verified against requirements using both directed tests and constrained random methodologies. Design support is expected from requirements definition through production release. Design documentation and configuration management are required.

This position is an onsite role, located in Plano, TX.

What You Will Do:

• Provide full lifecycle support of production quality FPGA designs for one or more major vendors and device families including: AMD (Xilinx), Altera, and Microchip (Microsemi).
• Generate FPGA designs for the following applications: multi-gigabit serial interfaces, Radio Frequency (RF) DSP, controls, data links, embedded processing and processor interfaces.
• Assist with architecture development of FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS).
• Design and code in VHDL for reliability and maintainability.
• Support design verification utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage.
• Understand and report execution status to the planned budget and schedule using an agile framework.
• Create complete documentation including requirements, verification plan, and user’s guides.
• Function as an individual contributor.
• Clearly present your work product to leadership.
• Engage in professional growth and development.

Qualifications You Must Have:

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 2 years of prior relevant experience.
• Experience to include at least 4 of the following:
• FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
• Experience with AMD (Xilinx), Altera and/or Microchip (Microsemi) devices and with tools such as AMD Vivado, Altera Quartus Prime Pro or Libero.
• Hands-on experience with integration and debug of FPGA/ASIC in a lab environment
• Experience with Git source code management, design reviews, and code release in a team development environment.
• Experience with Python or C programming
• Experience with CI/CD pipelines
• Experience with digital simulation such as Questa, RivieraPro or similar tools
• The ability to obtain and maintain a U.S. government issued security clearance post-start is required. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance.

Qualifications We Prefer:

• One or more advanced degrees in Electrical Engineering or a related Science, Technology, Engineering, or Mathematics (STEM) major. A suitable degree may be counted as 2 years of work experience.
• FPGA/ASIC design experience in one or more of the following areas:
• Embedded systems design using ARM, Microblaze, or NIOS processors
• Gigabit serial interfaces and multi-gigabit transceivers (MGTs)
• Constrained random verification in UVM using System Verilog
• Experience with High Level Synthesis (HLS)
• Experience with vector processors and/or GPUs
• Experience with timing closure, clock domain crossing and reset domain crossing analysis, and constraint development.
• Demonstrated ability to lead design efforts and/or small teams.
• Familiarity with AI LLM assisted workflows
• Knowledge of encryption/decryption standards such as AES, RSA, ECC, etc.

What We Offer:

Our values drive our actions, behaviors, and performance with a vision for a safer, more connected world. At RTX we value: Trust, Respect, Accountability, Collaboration, and Innovation.

As part of our commitment to maintaining a secure hiring process, candidates may be asked to attend select steps of the interview process in-person at one of our office locations, regardless of whether the role is designated as on-site, hybrid or remote.

The salary range for this role is 68,900 USD - 131,100 USD. The salary range provided is a good faith estimate representative of all experience levels. RTX considers several factors when extending an offer, including but not limited to, the role, function and associated responsibilities, a candidate’s work experience, location, education/training, and key skills.Hired applicants may be eligible for benefits, including but not limited to, medical, dental, vision, life insurance, short-term disability, long-term disability, 401(k) match, flexible spending accounts, flexible work schedules, employee assistance program, Employee Scholar Program, parental leave, paid time off, and holidays. Specific benefits are dependent upon the specific business unit as well as whether or not the position is covered by a collective-bargaining agreement.Hired applicants may be eligible for annual short-term and/or long-term incentive compensation programs depending on the level of the position and whether or not it is covered by a collective-bargaining agreement. Payments under these annual programs are not guaranteed and are dependent upon a variety of factors including, but not limited to, individual performance, business unit performance, and/or the company’s performance.This role is a U.S.-based role. If the successful candidate resides in a U.S. territory, the appropriate pay structure and benefits will apply.RTX anticipates the application window closing approximately 40 days from the date the notice was posted. However, factors such as candidate flow and business necessity may require RTX to shorten or extend the application window.

• medical
• dental
• vision
• life insurance
• short-term disability
• long-term disability
• 401(k) match
• flexible spending accounts
• flexible work schedules
• employee assistance program
• Employee Scholar Program
• parental leave
• paid time off
• holidays

• annual short-term and/or long-term incentive compensation programs depending on the level of the position and whether or not it is covered by a collective-bargaining agreement
• Payments under these annual programs are not guaranteed and are dependent upon a variety of factors including, but not limited to, individual performance, business unit performance, and/or the company’s performance
• Specific benefits are dependent upon the specific business unit as well as whether or not the position is covered by a collective-bargaining agreement

RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status, or any other applicable state or federal protected class. RTX provides affirmative action in employment for qualified Individuals with a Disability and Protected Veterans in compliance with Section 503 of the Rehabilitation Act and the Vietnam Era Veterans’ Readjustment Assistance Act.

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