Fpga Engineer

Actalent; United States; On-site; USD 110,000 - 152,000; Full time

Benefits offered by this job

Medical, dental & vision

401(k) Retirement Plan

Life Insurance

Time Off/Leave (PTO)

Job summary

Actalent in Irvine, CA is seeking an FPGA Engineer to lead the architecture, development, and verification of FPGA-based subsystems from concept through manufacturing. You will own the design and define the FPGA architecture, with RTL development in SystemVerilog or VHDL, collaborating with hardware teams.

This contract position is onsite in Irvine, offering competitive pay and a comprehensive benefits package.

Qualifications

• 10+ years FPGA RTL architecture, development, verification.
• Extensive experience with FPGA, Verilog, VHDL, SystemVerilog.
• Strong background in digital design and DSP.

Responsibilities

• Lead the architecture, development, and verification of FPGA-based subsystems.
• Own the design process from concept through qualification, verification, integration, and manufacturing.
• Define FPGA architecture and requirements.
• Develop RTL in SystemVerilog or VHDL.

Skills

FPGA

Verilog

VHDL

SystemVerilog

Vivado

Xilinx tools

Digital design

DSP

10+ years FPGA RTL

Tools

Vivado

Xilinx tools

Job description

Job Title: FPGA Engineer

Job Description

The FPGA Engineer will lead the architecture, development, and verification of FPGA-based subsystems. You will own the design from concept through qualification, verification, integration, and manufacturing. Additional responsibilities include defining FPGA architecture and requirements and developing RTL in SystemVerilog or VHDL.

Responsibilities

• Lead the architecture, development, and verification of FPGA-based subsystems.
• Own the design process from concept through qualification, verification, integration, and manufacturing.
• Define FPGA architecture and requirements.
• Develop RTL in SystemVerilog or VHDL.

Essential Skills

• Extensive experience with FPGA, Verilog, VHDL, SystemVerilog.
• Proficiency in using Vivado and Xilinx tools.
• Strong background in digital design and DSP.
• 10+ years of FPGA RTL architecture, development, and verification.

Job Type & Location

This is a Contract position based out of Irvine, CA.

Pay and Benefits

The pay range for this position is $80.00 - $110.00/hr.

Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this temporary role may include the following:

• Medical, dental & vision
• Critical Illness, Accident, and Hospital
• 401(k) Retirement Plan – Pre-tax and Roth post-tax contributions available
• Life Insurance (Voluntary Life & AD&D for the employee and dependents)
• Short and long-term disability
• Health Spending Account (HSA)
• Transportation benefits
• Employee Assistance Program
• Time Off/Leave (PTO, Vacation or Sick Leave)

Workplace Type

This is a fully onsite position in Irvine,CA.

Application Deadline

This position is anticipated to close on Aug 21, 2026.

The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.

If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing process due to a disability, please email [e-mail] for other accommodation options.

San Francisco Fair Chance Ordinance:

Pursuant to the San Francisco Fair Chance Ordinance, for all positions located in the city and county of San Francisco, we will consider for employment qualified applicants with arrest and conviction records.

Massachusetts Lie Detector:

It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.