FPGA Design Engineer

Normal Computing Corporation; New York (NY); On-site; USD 120,000 - 180,000; Full time

Job summary

Normal Computing seeks an FPGA Design Engineer to bridge RTL and physical silicon, bringing physics-inspired ASIC designs to life on FPGA platforms. You will support pre-silicon validation, early software development, and post-silicon bring-up with automated test environments.

You will work closely with silicon, EDA, and research teams across challenging hardware/software/physics domains. The role requires proven FPGA experience, SystemVerilog/VHDL mastery, and strong Python automation skills.

Qualifications

• Proven FPGA design experience from RTL through timing closure to validated hardware.
• Expert-level SystemVerilog or VHDL for synthesis with Xilinx Vivado knowledge.
• Hands-on PCIe, AXI/AHB, SPI, UART, JTAG interfaces experience.
• Strong Python for automation, test and build tooling.
• Solid lab bring-up and debugging skills on real hardware.

Responsibilities

• Lead FPGA platform ownership: select, procure, and bring-up FPGA prototyping platforms for pre-silicon validation and software development.
• Implement complex ASIC RTL onto FPGA targets with multi-clock-domain architectures and timing closure.
• Integrate in-house designs with third-party IP and vendor IP, especially AMD/Xilinx tools.
• Design, implement, and validate high-speed I/O focusing on PCIe in standard server environments.
• Build FPGA-based tester designs for silicon bring-up and characterization.
• Develop software layer around hardware: Python/C++ for hardware abstraction and automation.

Skills

SystemVerilog/VHDL

Vivado

PCIe

Python

Lab debugging

Tools

HAPS platforms

VCU118-class boards

Vivado IP Integrator

Job description

About Normal Computing

Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt.

We co-design the full stack: AI-native EDA systems in production with the world’s largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world’s leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing.

Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority.

The Role

Validating conventional silicon is a solved discipline. Validating silicon that computes with noise is not, and you will be the one who figures out how. As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early software development, and building the test infrastructure for post-silicon bring-up and characterization. Your scope spans the entire FPGA lifecycle: selecting hardware platforms, implementing complex RTL, debugging in the lab, and writing the software that drives it all, working daily with our silicon, EDA, and research teams.

What You’ll Own

• FPGA Platform Ownership: Lead the selection, procurement, and bring-up of FPGA prototyping platforms (e.g., HAPS, VCU118/VPK180-class boards, or custom hardware) for pre-silicon RTL validation and software development.

• RTL Implementation: Adapt and implement complex ASIC RTL onto FPGA targets, including multi-clock-domain architectures, CDC bridges, and timing closure on dense designs.

• IP Integration: Integrate in-house designs with third-party and vendor IP; serve as the expert on the AMD/Xilinx ecosystem (Vivado IP Integrator, transceivers, memory controllers).

• High-Speed Interfaces: Design, implement, and validate high-speed I/O with a focus on PCIe: our accelerators ship as PCIe cards in standard servers.

• Post-Silicon Validation: Build FPGA-based “tester” designs for silicon bring-up, device characterization, and automated test environments.

• Hardware-Software Stack: Develop the software layer around the hardware: Python/C++ hardware abstraction, register-map generation, and automated build and regression flows.

• Lab Debug: Root-cause complex timing and functional issues in real time using ILA/Vivado Analyzer, oscilloscopes, logic analyzers, and BER/eye-diagram characterization of high-speed links.

What Makes You a Great Fit

• Proven industry experience taking FPGA designs from RTL through timing closure to validated hardware, ideally in an ASIC prototyping, emulation, or high-growth hardware environment.

• Expert-level SystemVerilog and/or VHDL for synthesis, with deep proficiency in Xilinx Vivado (synthesis, place & route, timing closure, IP catalog).

• Hands-on experience implementing and debugging PCIe, plus AXI/AHB, SPI, UART, JTAG, and other common interfaces.

• Strong Python for automation, test, and build tooling.

• Strong board-level bring-up and lab debugging skills on real hardware.

• Startup mindset: you work independently, pivot quickly, and run at ambiguous problems that span hardware, software, and physics.

Bonus Points

• Verification frameworks like Cocotb, UVM, or OSVVM.

• Experience deploying ML models to FPGAs (hls4ml, FINN, or custom NN-to-RTL flows), or building real-time, sub-microsecond signal processing pipelines.

• Mixed-signal ASIC exposure: digital front-ends, ADC/DAC interfaces, or analog compute.

• SERDES tuning and signal integrity fundamentals.

• CI/CD for hardware (GitLab CI, Docker-based build and test).

_ Equal Employment Opportunity Statement _

Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.

_ Accessibility Accommodations _

Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at [e-mail].

_ Privacy Notice _

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